Hi, I have a question, my design uses two macros, I hardened the macros without a macro-level pdn.tcl, with just

set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PDN_CORE_RING) 0
set ::env(GLB_RT_MAXLAYER) 5

in the macro-level config.tcl. Now my top level flow fails in pdn stage, with message that the macros have no vdd and gnd ports. What are the ways/ the best way to do this now ? Thanks

Do you have the vdd and gnd nets defined in openlane config? I found it would fail to route macros without that

Thanks, I added the ports in RTL and nets in config.tcl, ut I am getting the below error now. There is no other information the logs mentioned, any idea what to do about this?

Type: stdcell, grid
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 153.600  offset: 16.320 
    Connect:  {met1 met4}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
-code 1 -level 0 -errorcode NONE -errorinfo {invalid command name "NULL"
    while executing
"builtin_unknown NULL setSpecial"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 builtin_unknown $args"
    (procedure "sta_unknown" line 36)
    invoked from within
"$bterm setSpecial"
    (procedure "export_opendb_power_pin" line 9)
    invoked from within
"export_opendb_power_pin $net_name "POWER""
    (procedure "export_opendb_power_pins" line 6)
    invoked from within
"export_opendb_power_pins"
    (procedure "opendb_update_grid" line 5)
    invoked from within
"opendb_update_grid"
    (procedure "apply" line 7)
    invoked from within
"apply $config"
    (procedure "pdngen::apply_pdn" line 14)
    invoked from within
"pdngen::apply_pdn $config_file $verbose "} -errorline 9
[CRIT] [PDNG-9999] Unexpected error: invalid command name "NULL"
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_pdn.tcl |& tee >&@stdout /project/openlane/darkriscv/runs/darkriscv/logs/floorplan/7-pdn.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check openroad  log file
[ERROR]: Dumping to /project/openlane/darkriscv/runs/darkriscv/error.log

Can you post a picture of your macro GDS?

Thanks, below is the png for the failing macro-recompilation, from the floorplan results- Please let me know if there are any issues due to resolution or something, thanks once again.

It looks empty?

Thanks, I have pushed. The repo is -

<https://github.com/bhawandeepsingh/darkriscv_in_openlane>

The project to build is darkriscv. All files are inside openlane/darkriscv directory. To build it, I export environment (ODK_ROOT and OPENLANE_ROOT) and from inside darkriscv_in_openlane, run

make darkriscv

Thanks once again

Why don't you follow the directory structure of the example project? Verilog should go under verilog/rtl not in openlane/block/src. Macros get put in gds and lef, so you don't need to copy under a macros subdir. Why the empty verilog files? Just specify as a macro by defining GDS, lef and the regular verilog as black box and it should work fine.

HI Prof. @Matthew Guthaus , thanks, I have changed directory structure and pushed. I had to choose something, presently all verilog files are in verilog/rtl and I just choose the ones I need in config.tcl. The other way I tried earlier was to keep all subprojects somewehere else and only my final top level project will go into the project directories. Please let me know if you will like any changes to this. It is going to change anyways, I will remove source files when I build top level project. 2. GLB_RT_MAXLAYER is given in openlane page for hardening macros

<https://openlane.readthedocs.io/en/latest/docs/source/hardening_macros.html#power-grid-pdn>

3. I will try what you are saying, remove the mentioned command(s) , retry and let know, thanks

Try with the defaults to eliminate problems...

Thanks Prof. @Matthew Guthaus. I got past that, Th difference from user_project_example was in rtl, `define USE_POWER_PINS was not defined. I removed the define in my darksoc.v as well. Now I am geeting an actual PDN error though -

[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd2 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vccd2.
[WARNING PSM-0030] Vsrc location at (5.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (21.600um, 223.040um).
[WARNING PSM-0030] Vsrc location at (145.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (172.800um, 223.040um).
[WARNING PSM-0030] Vsrc location at (285.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (329.400um, 223.040um).
[WARNING PSM-0030] Vsrc location at (285.520um, 150.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (329.400um, 223.040um).
[INFO PSM-0031] Number of nodes on net vccd2 = 4.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vccd2.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssd2 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssd2.
[WARNING PSM-0030] Vsrc location at (5.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (97.200um, 223.040um).
[WARNING PSM-0030] Vsrc location at (145.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 223.040um).
[WARNING PSM-0030] Vsrc location at (285.520um, 10.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 223.040um).
[WARNING PSM-0030] Vsrc location at (285.520um, 150.880um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 223.040um).
[INFO PSM-0031] Number of nodes on net vssd2 = 4.
[INFO PSM-0037] G matrix created sucessfully.
[WARNING PSM-0038] Unconnected PDN node on net vssd2 at location (405.000um, 223.040um), layer: 5.
[ERROR]: PDN generation failed.
[ERROR]: You may need to adjust your macro placements or PDN  offsets/pitches to power all standard cell rails (or other PDN stripes)  in your design.

This error comes with or without

set ::env(GLB_RT_MAXLAYER) 5

I am working on it now, I have pushed the latest files as well, thanks