Quick question While hardening macros has anyone ever come a

Question

Quick question While hardening macros has anyone ever come across `No clock nets have been found` error This is coming up during the CTS step despite having defined `CLOCK PORT` and `CLOCK PERIOD` in config tcl It seems to find the proper clock and move on because there are 0 sinks and then ends up not finding any <https github com AmoghLonkar openram testchip tree feature floorplan> is the link to the repo just in case Thanks

Matthew Guthaus · Answer

I specified only CLOCK PORT and not CLOCK NET and it works I m not sure what happens if you specify both simultaneously

Amogh Lonkar · Answer

Tried it both ways but still fails at that step

Matthew Guthaus · Answer

oh it looks like I had CLOCK TREE SYNTH set to false in my test

Matthew Guthaus · Answer

which is not good

Amogh Lonkar · Answer

It also passes that step for me if I set it to 0 but I would imagine we d need CTS to get a proper macro

Bhawandeep Singh Harsh · Answer

Same observation

Matthew Guthaus · Answer

Yeah the fanout is too high to not have a clock tree I had a fanout of 2 clock nets in my example

Amogh Lonkar · Answer

same

Matthew Guthaus · Answer

If you look at the DEF file which is passed to TritonCTS it definitely has the clk in port and net ```$ grep clk in openlane openram testchip runs openram testchip results placement openram testchip placement def clk in + NET clk in + DIRECTION INPUT + USE SIGNAL + PLACED 237130 1198000 N + LAYER met2 140 2000 140 2000 clk in PIN clk in + USE SIGNAL ```

Amogh Lonkar · Answer

TritonCTS finds the net but then skips because it has 0 sinks for some reason

Matthew Guthaus · Answer

If you look at the code the CTS script is openlane scripts tcl commands cts tcl which calls openroad openlane scripts openroad or cts tcl

Matthew Guthaus · Answer

Hrm check the Verilog It looks like it loads that

Matthew Guthaus · Answer

The synthesis output verilog

Matthew Guthaus · Answer

It has no fanout

Matthew Guthaus · Answer

openram testchip openlane openram testchip runs openram testchip results synthesis openram testchip synthesis v

Matthew Guthaus · Answer

your logic doesn t use a clock in SRAM IN

Matthew Guthaus · Answer

That is not synthesizable verilog

Matthew Guthaus · Answer

There isn t a single always posedge clk in

Matthew Guthaus · Answer

and so Yosys prunes away the memories even because their inputs are nothing

Amogh Lonkar · Answer

ah I see

Amogh Lonkar · Answer

thanks

Matthew Guthaus · Answer

In your verilog what are supposed to be the FFs

Matthew Guthaus · Answer

A FF with async reset should be ```always posedge clk or reset begin if reset begin mydff lt = 0 else begin mydff lt = din end end```

Amogh Lonkar · Answer

The FFs were supposed to hold the connections to the SRAMS but I hadn t synchronized or saved with a clock