Amogh Lonkar
05/17/2021, 11:56 PMNo clock nets have been found
error? This is coming up during the CTS step despite having defined CLOCK_PORT
and CLOCK_PERIOD
in config.tcl. It seems to find the proper clock and move on because there are 0 sinks and then ends up not finding any. https://github.com/AmoghLonkar/openram_testchip/tree/feature/floorplan is the link to the repo just in case. Thanks!Matthew Guthaus
05/18/2021, 12:03 AMAmogh Lonkar
05/18/2021, 12:03 AMMatthew Guthaus
05/18/2021, 12:07 AMAmogh Lonkar
05/18/2021, 12:09 AMBhawandeep Singh Harsh
05/18/2021, 12:10 AMMatthew Guthaus
05/18/2021, 12:10 AMAmogh Lonkar
05/18/2021, 12:11 AMMatthew Guthaus
05/18/2021, 12:12 AM$ grep clk_in openlane/openram_testchip/runs/openram_testchip/results/placement/openram_testchip.placement.def
- clk_in + NET clk_in + DIRECTION INPUT + USE SIGNAL + PLACED ( 237130 1198000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
- clk_in ( PIN clk_in ) + USE SIGNAL ;
Amogh Lonkar
05/18/2021, 12:15 AMMatthew Guthaus
05/18/2021, 12:16 AMAmogh Lonkar
05/18/2021, 12:22 AMMatthew Guthaus
05/18/2021, 12:27 AMalways @(posedge clk or reset) begin
if (reset) begin
mydff <= 0;
else begin
mydff <= din;
end
end
Amogh Lonkar
05/18/2021, 12:32 AM