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Quick question: While hardening macros, has anyone...
# openlane
a
Quick question: While hardening macros, has anyone ever come across 
No clock nets have been found
error? This is coming up during the CTS step despite having defined 
CLOCK_PORT
and 
CLOCK_PERIOD
in config.tcl. It seems to find the proper clock and move on because there are 0 sinks and then ends up not finding any. https://github.com/AmoghLonkar/openram_testchip/tree/feature/floorplan is the link to the repo just in case. Thanks!
m
I specified only CLOCK_PORT and not CLOCK_NET and it works. I'm not sure what happens if you specify both simultaneously...
a
Tried it both ways but still fails at that step.
m
oh, it looks like I had CLOCK_TREE_SYNTH set to false in my test
which is not good
a
It also passes that step for me if I set it to 0, but I would imagine we'd need CTS to get a proper macro
b
Same observation
m
Yeah, the fanout is too high to not have a clock tree. I had a fanout of 2 clock nets in my example
a
same
m
If you look at the DEF file, which is passed to TritonCTS, it definitely has the clk_in port and net:
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$ grep clk_in openlane/openram_testchip/runs/openram_testchip/results/placement/openram_testchip.placement.def
    - clk_in + NET clk_in + DIRECTION INPUT + USE SIGNAL + PLACED ( 237130 1198000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
    - clk_in ( PIN clk_in ) + USE SIGNAL ;
a
TritonCTS finds the net, but then skips because it has 0 sinks for some reason
m
If you look at the code, the CTS script is: openlane/scripts/tcl_commands/cts.tcl which calls openroad: openlane/scripts/openroad/or_cts.tcl
Hrm, check the Verilog. It looks like it loads that...
The synthesis output verilog
It has no fanout!
openram_testchip/openlane/openram_testchip/runs/openram_testchip/results/synthesis/openram_testchip.synthesis.v
your logic doesn't use a clock in SRAM_IN
That is not synthesizable verilog...
There isn't a single always @posedge clk_in
and so Yosys prunes away the memories even because their inputs are nothing
a
ah I see
thanks
m
In your verilog, what are supposed to be the FFs?
A FF with async reset should be:
Copy code
always @(posedge clk or reset) begin
if (reset) begin
  mydff <= 0;
else begin
  mydff <= din;
end
end
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a
The FFs were supposed to hold the connections to the SRAMS, but I hadn't synchronized or saved with a clock
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