any good advise to improve the design to make the optimisation routing to not take more that 64 iterations or any idea of how to hack it to have more than 64 iterations?

You might want to share the floorplan. What does the congestion look like? Is there enough room around macro pins? Do you have power stripes over some pins?

Hi I just add the floor plan (first image) and the placement (second image). I'm using all default in the openlane tool. ( I'm pretty new in hardware synthesis )

Yeah, set the PL_DENSITY_TARGET to spread things out. That is really congested

OK, thanks a lot, I was not sure If I can modify the density target. I'm going to try that now.

Unless you change the basic placement, that gets ignored. It's not very intuitive

ok, that fix the issue and increase the speed of syntheses. Thanks a lot, now I now that can play with the density.

@Ivan Rodriguez You can slightly increase the

GLB_RT_ADJUSTMENT

. This should get the design to route cleanly.

@Matthew Guthaus @Manar Abdelatty What are your rules for setting PL_BASIC_PLACEMENT, PL_DENSITY_TARGET and GLB_RT_ADJUSTMENT ? In which situations do you recommend which values?

@Philipp Gühring I don't really have any, sorry