Hi there, I'm new at here. I'm following openlane documentations, and yeah, I have a problem so I have joined 😅 I have a verilog file with no clock on it, only inputs and do something registers inside and outputs. When I try to to synthesize it, it is getting stucked at

5.22.2 Executing OPT_MERGE pass

phase. Here is my config.json:

{
  "DESIGN_NAME": "MY_MODULE",
  "VERILOG_FILES": "./designs/my_module/src/MY_MODULE.v",
  "CLOCK_PORT": "",
  "CLOCK_NET": "",
  "CLOCK_TREE_SYNTH": 0,
  "CLOCK_PERIOD": 0
}

There is no clock, the registers are getting updated by

always @(*)

block. Thanks!

post your design

It is a simple ALU. Here is the Verilog file:

module ALU(
    input [63:0] X,
    input [63:0] Y,
    input [3:0] OP,

    output [63:0] OUTPUT,
    output isEqual
);
    reg [127:0] RESULT;

    wire signed [63:0] X_signed = X;
    wire signed [63:0] Y_signed = Y;

    assign isEqual = X == Y;

    always @(*) begin
        case (OP)
            0:  RESULT <= X + Y; // add
            1:  RESULT <= X - Y; // sub
            2:  RESULT <= X & Y; // and
            3:  RESULT <= X | Y; // or
            4:  RESULT <= X ^ Y; // xor
            5:  RESULT <= X << Y; // shift left logical
            6:  RESULT <= X >> Y; // shift right logical
            7:  RESULT <= X_signed >>> Y; // shift right arithmetic
            8:  RESULT <= X * Y; // mul
            9:  RESULT <= X * Y; // mulh
            10: RESULT <= X / Y; // div
            11: RESULT <= X % Y; // rem
            12: RESULT <= (X_signed < Y_signed ? 1 : 0); // set less than (slt)
            13: RESULT <= (X < Y ? 1 : 0); // set less than (sltu)
        endcase
    end

    assign OUTPUT = OP == 9 ? RESULT[127:64] : RESULT[63:0];

endmodule

when you say "get stuck" - did the process die? or did you get bored waiting?

oh I see...

then I would put a `define in to cut out the * / operators and then you can get much faster results out of yosys and move on to the more ASIC side of things