Bhawandeep Singh Harsh
05/26/2021, 11:40 PMset ::env(DESIGN_IS_CORE) 0
set ::env(FP_PDN_CORE_RING) 0
set ::env(GLB_RT_MAXLAYER) 5 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
2. Added the below ports to my defintion and instantiation of the macro modules .
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
I have not done anything else. Specifically, I am not using any pdn.tcl for macros (as specified in the above-mentioned webpage). SInce design top is also going to be a macro inside user_project_wrapper, this also means that no pdn.tcl needs to be used for hardening design top either. Can someone please confirm or correct if this is enough/ correct for power connections upto design top? ThanksMatt Venn
05/27/2021, 8:47 AMBhawandeep Singh Harsh
05/27/2021, 9:46 AMYou can automate the power routing process in the core and macro level by reading this documentation. Otherwise, refer to this for more details about the syntax. In case you needed to create your own pdn.tcl then point to it using PDN_CFG.
So, I am following all the steps for automation @ https://openlane.readthedocs.io/en/latest/docs/source/advanced_power_grid_control.html#core-level. I am not using any pdn.tcl at all even for user_project_wrapper. The synthesis log prints that it is using default -
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /home/bhawandeepsingh/Desktop/darkriscv_in_openlane/PDK_ROOT/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_project_wrapper
Just want to confirm this is OK, to avoid any surprises later. Thanks a lot once again.Matt Venn
05/28/2021, 6:08 AM