Hi for hardening macros I have followed the instructions at open-source-silicon.dev #openlane

Hi, for hardening macros, I have followed the inst...

Bhawandeep Singh Harsh

05/26/2021, 11:40 PM

Hi, for hardening macros, I have followed the instructions at - https://openlane.readthedocs.io/en/latest/docs/source/advanced_power_grid_control.html#macro-level. Hence I have - 1. In my config.tcl, added -

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set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PDN_CORE_RING) 0
set ::env(GLB_RT_MAXLAYER) 5                                                                                                                                                                                                                                                                                                                    set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]

2. Added the below ports to my defintion and instantiation of the macro modules .

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`ifdef USE_POWER_PINS
    inout vdda1,	// User area 1 3.3V supply
    inout vdda2,	// User area 2 3.3V supply
    inout vssa1,	// User area 1 analog ground
    inout vssa2,	// User area 2 analog ground
    inout vccd1,	// User area 1 1.8V supply
    inout vccd2,	// User area 2 1.8v supply
    inout vssd1,	// User area 1 digital ground
    inout vssd2,	// User area 2 digital ground
`endif

I have not done anything else. Specifically, I am not using any pdn.tcl for macros (as specified in the above-mentioned webpage). SInce design top is also going to be a macro inside user_project_wrapper, this also means that no pdn.tcl needs to be used for hardening design top either. Can someone please confirm or correct if this is enough/ correct for power connections upto design top? Thanks

Matt Venn

05/27/2021, 8:47 AM

this is what I do and it's working fine

Matt Venn

05/27/2021, 8:47 AM

you should be able to see the power straps on your macro

Matt Venn

05/27/2021, 8:48 AM

and then after hardening in user project wrapper you will see the metal 5 horizontal straps dropping vias down onto the rails

Bhawandeep Singh Harsh

05/27/2021, 9:46 AM

Great, thanks

Bhawandeep Singh Harsh

05/28/2021, 6:05 AM

@Matt Venn Thanks a lot for the help so far, I have a flat design in user_project_wrapper now, last confirmation. https://openlane.readthedocs.io/en/latest/docs/source/chip_integration.html#power-routing says -

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You can automate the power routing process in the core and macro level by reading this documentation. Otherwise, refer to this for more details about the syntax. In case you needed to create your own pdn.tcl then point to it using PDN_CFG.

So, I am following all the steps for automation @ https://openlane.readthedocs.io/en/latest/docs/source/advanced_power_grid_control.html#core-level. I am not using any pdn.tcl at all even for user_project_wrapper. The synthesis log prints that it is using default -

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[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /home/bhawandeepsingh/Desktop/darkriscv_in_openlane/PDK_ROOT/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_project_wrapper

Just want to confirm this is OK, to avoid any surprises later. Thanks a lot once again.

Matt Venn

05/28/2021, 6:08 AM

Looks ok. I only needed to mess with pdn in mpw1. Everything has worked for me so far in mpw2 by following the user proj example

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