Hi I am presently hardening the design top I am getting rout open-source-silicon.dev #openlane

Hi, I am presently hardening the design top. I am ...

Bhawandeep Singh Harsh

05/27/2021, 10:24 AM

Hi, I am presently hardening the design top. I am getting routing issues.

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Reading DEF file: /project/openlane/darksocv/runs/darksocv/tmp/routing/17-addspacers.obs.def
Notice 0: Design: darksocv
Notice 0: 		Created 100000 Insts
Notice 0: 		Created 200000 Insts
Notice 0: 		Created 300000 Insts
Notice 0: 		Created 400000 Insts
Notice 0: 		Created 500000 Insts
Notice 0: 		Created 600000 Insts
Notice 0: 		Created 700000 Insts
Notice 0: 		Created 800000 Insts
Notice 0: 		Created 100000 Nets
Notice 0: 		Created 200000 Nets
Notice 0:     Created 98 pins.
Notice 0:     Created 851766 components and 4476919 component-terminals.
Notice 0:     Created 8 special nets and 0 connections.
Notice 0:     Created 260983 nets and 1069846 connections.
Notice 0: Finished DEF file: /project/openlane/darksocv/runs/darksocv/tmp/routing/17-addspacers.obs.def
Min routing layer: 2
Max routing layer: 5
Global adjustment: 0.3
Unidirectional routing: true
Grid origin: (0, 0)
[INFO GRT-0004] #DB Obstructions: 1
[INFO GRT-0005] #DB Obstacles: 31522005
[INFO GRT-0006] #DB Macros: 2
[INFO GRT-0017] Found 0 clock nets
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 16389
[INFO GRT-0018] Processing 15554833 obstacles on layer 1
[INFO GRT-0019] Processing 3585620 obstacles on layer 2
[INFO GRT-0020] Processing 299 obstacles on layer 3
[INFO GRT-0021] Processing 304 obstacles on layer 4
[INFO GRT-0022] Processing 269 obstacles on layer 5
[INFO GRT-0019] Reducing resources of layer 1 by 99%
[INFO GRT-0020] Reducing resources of layer 2 by 30%
[INFO GRT-0021] Reducing resources of layer 3 by 30%
[INFO GRT-0022] Reducing resources of layer 4 by 30%
[INFO GRT-0023] Reducing resources of layer 5 by 30%
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_groute.tcl |& tee >&@stdout /project/openlane/darksocv/runs/darksocv/logs/routing/18-fastroute.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: kill signal                                                                                                                                                                                     < DRC - LVS - Antenna reports not found >                                                                                                                                 
                                                                                                                                                                                                                 [ERROR]: Flow Failed.
    while executing
"try_catch openroad -exit $::env(SCRIPTS_DIR)/openroad/or_groute.tcl |& tee $::env(TERMINAL_OUTPUT) $saveLOG"
    (procedure "global_routing_fastroute" line 5)
    invoked from within
"global_routing_fastroute"
    (procedure "global_routing" line 10)
    invoked from within
"global_routing"
    (procedure "run_routing" line 27)
    invoked from within
"run_routing"
    (procedure "run_non_interactive_mode" line 19)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 223)
make[1]: *** [Makefile:43: darksocv] Error 1
make[1]: Leaving directory '/home/bhawandeepsingh/Desktop/darkriscv_in_openlane/openlane'
make: *** [Makefile:71: darksocv] Error 2

I see it is exiting for some reason, but I do not know what caused the exception. I am not clear what are "obstacles" in this context and what I need to do about this. I tried to make my memory half and even quarter the size; that should decrease both the number of transistors as well as the congestion of memory-data wires, but I am still getting the same error. I also tried changing both global and detailed router types, but no change. I have set PL_ROUTABILITY_DRIVEN. I have also tried changing GLB_RT_ADJUSTMENT. Nothing has solved the issue. Can anyone help with what this is and what I can do about this ? Thanks

Matt Venn

05/27/2021, 10:40 AM

as openlane works, it saves pngs of various states

Matt Venn

05/27/2021, 10:42 AM

can you post the macro placement png

Matt Venn

05/27/2021, 10:47 AM

openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def.png

Bhawandeep Singh Harsh

05/27/2021, 1:05 PM

Thanks, please find it attached

Matt Venn

05/27/2021, 2:56 PM

I'm surprised that little one got hardened. It looks too small for power routing

Matt Venn

05/27/2021, 2:56 PM

can you get a result if you just use the big macro?

Bhawandeep Singh Harsh

05/27/2021, 4:26 PM

Thanks, I commented out darkuart instantiation in rtl, removed the gds, elf from config.tcl and macro from macro placement file. Still got the same error.

Bhawandeep Singh Harsh

05/27/2021, 4:28 PM

The floorpln png image looked as -

Matt Venn

05/27/2021, 4:36 PM

So you are hardening some macros into another macro that you are going to put into upw?

Matt Venn

05/27/2021, 4:38 PM

You will have to make sure you are dealing with the pdn. I don't know how that works.

Matt Venn

05/27/2021, 4:38 PM

I would avoid this extra layer of possible

Matt Venn

05/27/2021, 4:38 PM

Every level of macro you lose a layer to route on

Bhawandeep Singh Harsh

05/27/2021, 6:21 PM

Thanks, yes, I have macros in my design top (which is a macro itself)

Bhawandeep Singh Harsh

05/27/2021, 6:21 PM

Does that mean I should have no macros at all insie my design top ?

Matt Venn

05/27/2021, 6:36 PM

I wouldn't. But it can make wiring harder

Matt Venn

05/27/2021, 6:36 PM

Because you have to do all the routing and instanciation inside upw

Bhawandeep Singh Harsh

05/27/2021, 7:27 PM

Prof. @Matthew Guthaus I am referring to this chat for macros, thanks

Matthew Guthaus

05/27/2021, 7:47 PM

@Bhawandeep Singh Harsh so you have wrapper -> top -> blocks? Yes, omit top

Bhawandeep Singh Harsh

05/27/2021, 8:13 PM

Thanks Prof. @Matthew Guthaus. I will use macros for the inner modules, and use rtl for design top inside the wrapper for synthesis. One question I have is, how to specify the heirarchical path for the macros in macro.cfg ?

Matthew Guthaus

05/27/2021, 8:16 PM

@Bhawandeep Singh Harsh I believe the macros have to be at the top level, you can't refer to them down in the hierarchy

Matthew Guthaus

05/27/2021, 8:16 PM

I could be wrong though, try it out!

Matthew Guthaus

05/27/2021, 8:17 PM

It only takes a minute to try

Bhawandeep Singh Harsh

05/27/2021, 8:39 PM

Thanks, I have already tried the below three and none worked (Here core0 refers to the instance name for darkriscv that is supposed to be a macro inside darksocv whose instance name is design_top)) - 1.

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core0 800 400 N

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design_top.core0 800 400 N

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desing_top/core0 800 400 N

This will leave me with two options - either 1. bring the macros outside darksocv - possible but very error prone due to the way RTL Is wrriten, I can show and explain or 2. Not use macros at all

Bhawandeep Singh Harsh

05/28/2021, 5:38 AM

Thanks a lot @Matt Venn, I have made changes to remove macros, I have a flat design now, I still have routing issues, though different ones, as below -

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Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/17-addspacers.def
Min routing layer: 2
Max routing layer: 6
Global adjustment: 0.2
Unidirectional routing: true
Grid origin: (0, 0)
[INFO GRT-0004] #DB Obstructions: 0
[INFO GRT-0005] #DB Obstacles: 31494557
[INFO GRT-0006] #DB Macros: 0
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vccd1 has wires outside die area
[WARNING GRT-0022] Net vssd1 has wires outside die area
[WARNING GRT-0022] Net vssd1 has wires outside die area
[WARNING GRT-0022] Net vssd1 has wires outside die area
[WARNING GRT-0022] Net vssd1 has wires outside die area
[WARNING GRT-0022] Net vssd1 has wires outside die area
[WARNING GRT-0022] Net vccd2 has wires outside die area
[WARNING GRT-0022] Net vccd2 has wires outside die area
[WARNING GRT-0022] Net vccd2 has wires outside die area
[WARNING GRT-0022] Net vssd2 has wires outside die area
[WARNING GRT-0022] Net vssd2 has wires outside die area
[WARNING GRT-0022] Net vdda1 has wires outside die area
[WARNING GRT-0022] Net vssa1 has wires outside die area
[WARNING GRT-0022] Net vssa1 has wires outside die area
[WARNING GRT-0022] Net vssa1 has wires outside die area
[WARNING GRT-0022] Net vssa1 has wires outside die area
[WARNING GRT-0022] Net vssa1 has wires outside die area
[WARNING GRT-0022] Net vdda2 has wires outside die area
[WARNING GRT-0022] Net vdda2 has wires outside die area
[WARNING GRT-0022] Net vdda2 has wires outside die area
[WARNING GRT-0022] Net vdda2 has wires outside die area
[WARNING GRT-0022] Net vssa2 has wires outside die area
[WARNING GRT-0022] Net vssa2 has wires outside die area
[WARNING GRT-0022] Net vssa2 has wires outside die area
[WARNING GRT-0022] Net vssa2 has wires outside die area
[WARNING GRT-0022] Net vssa2 has wires outside die area
[WARNING GRT-0022] Net vssa2 has wires outside die area
[INFO GRT-0017] Found 0 clock nets
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 16391
[INFO GRT-0018] Processing 15726404 obstacles on layer 1
[INFO GRT-0019] Processing 3611531 obstacles on layer 2
[INFO GRT-0022] Processing 154 obstacles on layer 5
[INFO GRT-0023] Processing 154 obstacles on layer 6
[INFO GRT-0020] Reducing resources of layer 1 by 99%
[INFO GRT-0021] Reducing resources of layer 2 by 20%
[INFO GRT-0022] Reducing resources of layer 3 by 20%
[INFO GRT-0023] Reducing resources of layer 4 by 20%
[INFO GRT-0024] Reducing resources of layer 5 by 20%
[INFO GRT-0025] Reducing resources of layer 6 by 20%
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_groute.tcl |& tee >&@stdout /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/routing/18-fastroute.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation

Any idea what causes these wires to go out of die and what can I do about this ? Is that the (only) issue causing segmentation fault ? There is no more information in the logs. Thanks

Bhawandeep Singh Harsh

05/28/2021, 9:08 AM

There is something very fishy. I reduced memory size from 2K 32 bit locations to 16 32 bit locations just to see what happens. Routing still fails with below -

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Update congestion history type 2
[INFO] iteration 10, enlarge 39, costheight 69, threshold 0 via cost 0 
[INFO] log_coef 0.378039, healingTrigger 3 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 757215
[Overflow Report] Max H Overflow: 71
[Overflow Report] Max V Overflow: 73
[Overflow Report] Max Overflow  : 73
[Overflow Report] Num Overflow e: 11030
[Overflow Report] H   Overflow  : 257368
[Overflow Report] V   Overflow  : 274229
[Overflow Report] Final Overflow: 531597

Update congestion history type 2
[INFO] iteration 11, enlarge 39, costheight 76, threshold 0 via cost 0 
[INFO] log_coef 0.378039, healingTrigger 3 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 757217
[Overflow Report] Max H Overflow: 70
[Overflow Report] Max V Overflow: 74
[Overflow Report] Max Overflow  : 74
[Overflow Report] Num Overflow e: 11030
[Overflow Report] H   Overflow  : 257364
[Overflow Report] V   Overflow  : 274229
[Overflow Report] Final Overflow: 531593

There is something wierd going on.

Matthew Guthaus

05/28/2021, 2:00 PM

@Bhawandeep Singh Harsh what is your placement and density setting? I've discussed this before...

Matthew Guthaus

05/28/2021, 2:47 PM

@Bhawandeep Singh Harsh also, i suggest you don't P&R the memory as we discussed before

Bhawandeep Singh Harsh

05/28/2021, 4:10 PM

Thanks Prof. @Matthew Guthaus I have the below -

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set ::env(FP_CORE_UTIL) "40"
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]

It is still the same even if I reduce memory size to 16 words, but I will change to an openram memory next, is there a tested reference I can use ? Thanks

Matthew Guthaus

05/28/2021, 4:10 PM

What is PL_BASIC_PLACEMENT?

Matthew Guthaus

05/28/2021, 4:11 PM

If that is true, it will ignore the density

Bhawandeep Singh Harsh

05/28/2021, 4:27 PM

It is 0 by default, I did not change it. I have cleared it to 0 explicitly now.

Matthew Guthaus

05/28/2021, 4:28 PM

did their script set it to somethign that is not default? 0 is default for OpenLane, but it doesn't mean that carvel didn't set it

Matthew Guthaus

05/28/2021, 4:28 PM

caravel != openlane

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