Bhawandeep Singh Harsh
05/28/2021, 9:39 AMLocal interconnect minimum area < 0.0561um^2 (li.6)
I tried to look for some variables/ switches that can control it, but does not look like any. 2 questions - 1, My design is not very big. What causes these ? 2. What can be done about these ? This is my config.tcl
set script_dir [file dirname [file normalize [info script]]]
# User config
set ::env(DESIGN_NAME) user_project_wrapper
# Change if needed
#set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v \
$script_dir/../../verilog/rtl/darksocv.v \
$script_dir/../../verilog/rtl/darkriscv.v \
$script_dir/../../verilog/rtl/darkuart.v"
# Fill this
set ::env(CLOCK_PERIOD) "100"
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set ::env(SYNTH_FLAT_TOP) 1
set ::env(SYNTH_MAX_TRANS) "0.2"
set ::env(FP_CORE_UTIL) "40"
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
set ::env(PL_ROUTABILITY_DRIVEN) 1
set ::env(GLB_RT_ADJUSTMENT) .20
set ::env(FP_PDN_AUTO_ADJUST) "1"
set ::env(DESIGN_IS_CORE) 1
set ::env(FP_PDN_CORE_RING)
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_PDN_CORE_RING_VWIDTH) 3
set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH)
set ::env(FP_PDN_CORE_RING_VOFFSET) 14
set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
set ::env(FP_PDN_VWIDTH) 3
set ::env(FP_PDN_HWIDTH) 3
set ::env(FP_PDN_VOFFSET) 0
set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
set ::env(FP_PDN_VPITCH) 180
set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
ThanksMatthew Guthaus
05/28/2021, 2:46 PMBhawandeep Singh Harsh
05/28/2021, 4:15 PMMatthew Guthaus
05/28/2021, 4:20 PMBhawandeep Singh Harsh
05/28/2021, 4:26 PMMatthew Guthaus
05/28/2021, 4:26 PMBhawandeep Singh Harsh
05/28/2021, 4:29 PMMatthew Guthaus
05/28/2021, 4:30 PMBhawandeep Singh Harsh
05/28/2021, 4:31 PMset ::env(FP_CORE_UTIL) "40"
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
set ::env(PL_ROUTABILITY_DRIVEN) 1
Matthew Guthaus
05/28/2021, 4:32 PMBhawandeep Singh Harsh
05/28/2021, 4:39 PMMatthew Guthaus
05/28/2021, 5:01 PMBhawandeep Singh Harsh
05/28/2021, 5:03 PMMatthew Guthaus
05/28/2021, 8:30 PMBhawandeep Singh Harsh
05/28/2021, 8:31 PMMatthew Guthaus
05/28/2021, 8:31 PMBhawandeep Singh Harsh
05/28/2021, 8:32 PMMatthew Guthaus
05/28/2021, 8:52 PMBhawandeep Singh Harsh
05/28/2021, 9:31 PMMatthew Guthaus
05/28/2021, 9:35 PMBhawandeep Singh Harsh
05/28/2021, 9:40 PMset ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
and also decreases. Is this the right thing to do ?Matthew Guthaus
05/28/2021, 9:51 PMBhawandeep Singh Harsh
05/28/2021, 10:14 PMset ::env(PL_BASIC_PLACEMENT) "0"
Matthew Guthaus
05/28/2021, 10:17 PMBhawandeep Singh Harsh
05/28/2021, 10:18 PMMatthew Guthaus
05/28/2021, 10:20 PMBhawandeep Singh Harsh
05/28/2021, 10:22 PMset ::env(PL_BASIC_PLACEMENT) 0
Matthew Guthaus
05/28/2021, 10:23 PMBhawandeep Singh Harsh
05/28/2021, 10:24 PMset ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
and also decreases. Is this the right thing to do ?Matthew Guthaus
05/28/2021, 10:24 PMBhawandeep Singh Harsh
05/28/2021, 10:26 PMMatthew Guthaus
05/28/2021, 10:27 PMBhawandeep Singh Harsh
05/28/2021, 10:31 PMMatthew Guthaus
05/28/2021, 10:34 PMBhawandeep Singh Harsh
05/28/2021, 10:46 PMMatthew Guthaus
05/28/2021, 10:48 PMBhawandeep Singh Harsh
05/28/2021, 10:48 PMLocal interconnect minimum area < 0.0561um^2 (li.6)
All DRC vilations are of this type. I am not sure what this means, what causes this and how to go aheadMatthew Guthaus
05/28/2021, 10:48 PMBhawandeep Singh Harsh
05/28/2021, 10:48 PMMatthew Guthaus
05/28/2021, 10:48 PMBhawandeep Singh Harsh
05/28/2021, 10:49 PMMatthew Guthaus
05/28/2021, 10:51 PMBhawandeep Singh Harsh
05/28/2021, 10:51 PMHieu Bui
05/29/2021, 3:59 AMBhawandeep Singh Harsh
05/29/2021, 3:59 AMHieu Bui
05/29/2021, 4:17 AMBhawandeep Singh Harsh
05/29/2021, 6:28 AMHieu Bui
05/29/2021, 6:33 AMBhawandeep Singh Harsh
05/29/2021, 6:34 AMHieu Bui
05/29/2021, 6:35 AM$ cat OPENLANE_VERSION
openlane v0.15
$ cat PDK_SOURCES
skywater-pdk bb2f842ac8d1b750677ca25bc71fb312859edb82
open_pdks 7e29496eecf3ee8e1766f1b7f9441f97204d4735
Bhawandeep Singh Harsh
05/29/2021, 6:36 AM$ cat OPENLANE_VERSION
openlane v0.15
$ cat PDK_SOURCES
-ne skywater-pdk
bb2f842ac8d1b750677ca25bc71fb312859edb82
-ne open_pdks
7e29496eecf3ee8e1766f1b7f9441f97204d4735
Hieu Bui
05/29/2021, 6:37 AMBhawandeep Singh Harsh
05/29/2021, 6:38 AMHieu Bui
05/29/2021, 6:39 AMBhawandeep Singh Harsh
05/29/2021, 6:42 AMHieu Bui
05/29/2021, 7:17 AMBhawandeep Singh Harsh
05/29/2021, 7:18 AMHieu Bui
05/29/2021, 7:23 AMBhawandeep Singh Harsh
05/29/2021, 7:26 AMHieu Bui
05/29/2021, 7:29 AMBhawandeep Singh Harsh
05/29/2021, 8:15 AMHieu Bui
05/29/2021, 10:00 AMsudo chmod 666 /var/run/docker.sock
The command to do this is:
$ gpasswd -a <your account> docker
After that, you need to log out then log in.Bhawandeep Singh Harsh
05/29/2021, 10:55 AMmake <project>
I installed the pdk using
make pdk
ALI AHMED
06/03/2021, 8:22 PMAireen Amir Jalal
06/04/2021, 5:51 AM