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Hi, I have ~70k DRC violations, all of the same ty...
# openlane
b
Hi, I have ~70k DRC violations, all of the same type -
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Local interconnect minimum area < 0.0561um^2 (li.6)
I tried to look for some variables/ switches that can control it, but does not look like any. 2 questions - 1, My design is not very big. What causes these ? 2. What can be done about these ? This is my config.tcl
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set script_dir [file dirname [file normalize [info script]]]

# User config
set ::env(DESIGN_NAME) user_project_wrapper

# Change if needed
#set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(VERILOG_FILES) "\
	$script_dir/../../caravel/verilog/rtl/defines.v \
	$script_dir/../../verilog/rtl/user_project_wrapper.v \
	$script_dir/../../verilog/rtl/darksocv.v \
	$script_dir/../../verilog/rtl/darkriscv.v \
	$script_dir/../../verilog/rtl/darkuart.v"

# Fill this
set ::env(CLOCK_PERIOD) "100"
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set ::env(SYNTH_FLAT_TOP) 1                            
set ::env(SYNTH_MAX_TRANS) "0.2"

set ::env(FP_CORE_UTIL) "40"
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]

set ::env(PL_ROUTABILITY_DRIVEN) 1
set ::env(GLB_RT_ADJUSTMENT) .20

set ::env(FP_PDN_AUTO_ADJUST) "1"

set ::env(DESIGN_IS_CORE) 1
set ::env(FP_PDN_CORE_RING) 

set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_PDN_CHECK_NODES) 0

set ::env(FP_PDN_CORE_RING_VWIDTH) 3 
set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH) 
set ::env(FP_PDN_CORE_RING_VOFFSET) 14 
set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET) 
set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 
set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)

set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]

set ::env(FP_PDN_VWIDTH) 3 
set ::env(FP_PDN_HWIDTH) 3 
set ::env(FP_PDN_VOFFSET) 0 
set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET) 
set ::env(FP_PDN_VPITCH) 180 
set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)

set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0

set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}
Thanks
m
Does the placement look congested?
Specifically, check your setting for PL_BASIC_PLACEMENT. It should be False.
b
PL_BASIC_PLACEMENT is 0 by default, I am not changing it. I have started a new build with it explicitly reset to 0.
m
Check the value. Do they set it somewhere?
Also view the density to see if it is too dense
b
HI Prof. @Matthew Guthaus Please find the png attached. Thanks
m
That is very dense
It basically doesn't fit
It is also not spread out very well. I think the setting is wrong. Otherwise it would be using that space in the corners
b
Let me try decreasing FP_CORE_UTIL a little more keeping PL_TARGET_DENSITY same or decreasing that as well.
m
check the setting..
just check the setting...
b
Thanks, I am using these -
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set ::env(FP_CORE_UTIL) "40"
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
set ::env(PL_ROUTABILITY_DRIVEN) 1
m
I don't know how to say it any other way. Check the setting of PL_BASIC_PLACEMENT
It may be set to the nondefaut value by the caravel scripts
b
Thanks, I have another build going with it explicitly reset to 0.
Thanks, Prrof. @Matthew Guthaus . Its exactly same number of violations with PL_BASIC_PLACEMENT explicitly cleared to 0 also
m
Ok. Then you need to decrease the density some other way
b
Thanks, I am triyng that next.
DRC violations increased by a couple thousand
m
What does the placement look like now?
b
user_project_wrapper.placement.def.png
m
That is still really dense and not spread out
it's no different than before?
b
Placement is different, # of DRC violations is very slightly more
Let me try changing FP_CORE_UTIL and PL_TARGET_DENSITY futher
m
The placement is not very different
It is still roughly the same utilization
b
Decreasing FP_CORE_UTIL and PL_TARGET_DENSITY further increased DRC violations slightly
m
why isn't it spreading it out more? your PL_TARGET_DENSITY is being ignored
b
Thanks, a confirmation if I am doing it right. I am decreasing the FP_CORE_UTIL. PL_TARGET_DENSITY is in terms of FP_CORE_UTIL as -
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set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
and also decreases. Is this the right thing to do ?
m
It still looks like PL_BASIC_PLACEMENT is true to me
shrug you will have to debug this. Does it output anything about the density? Or the global routing? You can also change the GLOBAL_RT_ADJUSTMENT
b
Thanks, this is from the config.tcl dumped in the runs directory
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set ::env(PL_BASIC_PLACEMENT) "0"
m
That is probably setting it as a string
I'm not sure though. You'll need to learn to debug...
b
Sure, thanks
m
Yes, every other example does: set ::env(PL_BASIC_PLACEMENT) 0
b
I have done the same as well, given 0 without quotes. I think both with and without quotes work, I have not seen that make a difference for non-string values. My setting is -
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set ::env(PL_BASIC_PLACEMENT) 0
m
How else can you debug why it isn't spreading things out?
b
Is my understanding correct - I am decreasing the FP_CORE_UTIL. PL_TARGET_DENSITY is in terms of FP_CORE_UTIL as -
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set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
and also decreases. Is this the right thing to do ?
m
Why do you think you would do that?
What is the purpose of that expr
(I'm not saying it's wrong, I'm asking why)
b
My understanding is that decreasing FP_CORE_UTIL means logic cells will take less area, leaving more area for routing. DEcreasing PL_TARGET_DENSITY, will decrease density, making the layout sparse/ spread out and leaving more room for routing.
The expression I just took from example.
m
FP_CORE_UTIL determines the floorplan utilization. It makes the floorplan bigger compared to the total cell area if you have a relative sized floorplan
PL_TARGET_DENSITY tells the placer how much local density should be in a given area. So it tries to spread the cells out more inside the area. It has to be bigger than FP_CORE_UTIL because even if everything is perfectly distributed, the best you could do is FP_CORE_UTIL for the local density everywhere
What happens in that expression now?
You are fixing them so that PL_TARGET_DENSITY is always percent more than the other
Is that a good number?
Does your log say anything during placement about density?
b
The run log does not say anything about error or not, it just prints the value used, then the area and then the new value it calculated, that is very slightly more than actual value.
m
What else can you try?
b
I have tried changing FP_CORE_UTIL, PL_TARGET_DENSITY, GLB_RT_ADJUSTMENT and PL_ROUTABILITY_DRIVEN.
m
What ELSE can you try?
b
The violation is -
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Local interconnect minimum area < 0.0561um^2 (li.6)
All DRC vilations are of this type. I am not sure what this means, what causes this and how to go ahead
m
Where do you get that error?
b
I am checking all variables, if something sounds like it will impact this.
m
In the layout
b
The flow completes, it says there are DRC violations.
m
look at the layout and see where the errors are
debug it
you can see why they happen
ok, i need to go for now
b
Sure, thanks
h
Hi Bhawandeep, have you commit your config to your github? I can take a look at it.
b
I will do it now, thanks
Thanks a lot once again, pushed just now, the link is - https://github.com/bhawandeepsingh/darkriscv_in_openlane.
h
Thanks. I will take a look rightnow :)
I have run your script and I do not get any DRC problem. However, LVS failed.
Which version of the PDK and the openlane that you are using? I am using openlane v0.15 and the pdk commit from Caravel_lite and there are no DRC error. The LVS error might be of the power & ground net. there are 3 net different between the verilog netlist and the layout.
b
Thanks, let me see the versions.
PDK version - 1.0.156
h
you can cd to 'openlane/user_project_wrapper/runs/user_project_wrapper' and run 'cat PDK_SOURCES' and 'cat OPENLANE_VERSION'
b
I do not see Openlane version anywhere in the OPenlane_root directory. The build log shows - Version: v0.15
h
These are mine:
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$ cat OPENLANE_VERSION 
openlane v0.15
$ cat PDK_SOURCES 
skywater-pdk bb2f842ac8d1b750677ca25bc71fb312859edb82
open_pdks 7e29496eecf3ee8e1766f1b7f9441f97204d4735
b
Thanks, I get -
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$ cat OPENLANE_VERSION 
openlane v0.15
$ cat PDK_SOURCES 
-ne skywater-pdk 
bb2f842ac8d1b750677ca25bc71fb312859edb82
-ne open_pdks 
7e29496eecf3ee8e1766f1b7f9441f97204d4735
h
I also think that you should harden the darksocv as a macro first, then assemble it into the user_project_wrapper because the user_project_wrapper are specific to Caravel test harness.
b
I will try that next, 1 question - I see -ne in my results above, but not in your results, any idea what that is and if that makes a difference
h
For that I have no idea. Are you using the tools from the docker image or you build the tool yourself?
b
I am using docker, but I am using docker first time, so highly likely I am doing something wrong there.
Are you using docker image or you build yourself ?
h
I use the docker image from openlane
b
Thanks, I have another question, even in my run it says no DRC violations after detailed routing and then no LVS mismatches. But after that I have violations in magic drc, Do you see no DRC violations in drc after detailed routing or in magic drc ?
h
There is no drc violation after detailed routing
b
Oh, then there is a disconnect, in my run also, there are no drc violations after detailed routing, no lvs violations, but after that magic drc gives violations.
Thanks, for you did the flow reach completion without erroring out ? Were there only 3 lvs violations after flow completion ?
h
The flow does not complete. It stops at the lvs error.
Maybe you can try with a clean version of the tools and PDK. checkout your github project to a new folder and then install openlane and pdk as explained in the document.
You can also try to run the default caravel_user_project to see if there is any problem with the pdk and the tool. It should work.
b
I have drc violations in user_project_example also. Something about tools is probably messed up
h
How do you open the project in Magic?
Did you build the pdk by running "make pdk-nonnative"?
In your setup, you should add your account to docker group and remove this line:
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sudo chmod 666 /var/run/docker.sock
The command to do this is:
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$ gpasswd -a <your account> docker
After that, you need to log out then log in.
Also, I do not use the full Caravel test harness. Caravel Lite is good enough for me.
b
I do not open the project in magic, the step is run as part of
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make <project>
I installed the pdk using
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make pdk
a
@Aireen Amir Jalal please read the thread, may be helpful with the versions and caravel integration.
👀 1
a
Sure Sir @ALI AHMED!
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