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# openlane
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Bhawandeep Singh Harsh
05/28/2021, 9:39 AMHi, I have ~70k DRC violations, all of the same type -
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Local interconnect minimum area < 0.0561um^2 (li.6) Copy code
set script_dir [file dirname [file normalize [info script]]]
# User config
set ::env(DESIGN_NAME) user_project_wrapper
# Change if needed
#set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v \
$script_dir/../../verilog/rtl/darksocv.v \
$script_dir/../../verilog/rtl/darkriscv.v \
$script_dir/../../verilog/rtl/darkuart.v"
# Fill this
set ::env(CLOCK_PERIOD) "100"
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set ::env(SYNTH_FLAT_TOP) 1
set ::env(SYNTH_MAX_TRANS) "0.2"
set ::env(FP_CORE_UTIL) "40"
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
set ::env(PL_ROUTABILITY_DRIVEN) 1
set ::env(GLB_RT_ADJUSTMENT) .20
set ::env(FP_PDN_AUTO_ADJUST) "1"
set ::env(DESIGN_IS_CORE) 1
set ::env(FP_PDN_CORE_RING)
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_PDN_CORE_RING_VWIDTH) 3
set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH)
set ::env(FP_PDN_CORE_RING_VOFFSET) 14
set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
set ::env(FP_PDN_VWIDTH) 3
set ::env(FP_PDN_HWIDTH) 3
set ::env(FP_PDN_VOFFSET) 0
set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
set ::env(FP_PDN_VPITCH) 180
set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}m
Matthew Guthaus
05/28/2021, 2:46 PMDoes the placement look congested?
Specifically, check your setting for PL_BASIC_PLACEMENT. It should be False.
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Bhawandeep Singh Harsh
05/28/2021, 4:15 PMPL_BASIC_PLACEMENT is 0 by default, I am not changing it. I have started a new build with it explicitly reset to 0.
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Matthew Guthaus
05/28/2021, 4:20 PMCheck the value. Do they set it somewhere?
Also view the density to see if it is too dense
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Bhawandeep Singh Harsh
05/28/2021, 4:26 PMHI Prof. @Matthew Guthaus Please find the png attached. Thanks
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Matthew Guthaus
05/28/2021, 4:26 PMThat is very dense
It basically doesn't fit
It is also not spread out very well. I think the setting is wrong. Otherwise it would be using that space in the corners
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Bhawandeep Singh Harsh
05/28/2021, 4:29 PMLet me try decreasing FP_CORE_UTIL a little more keeping PL_TARGET_DENSITY same or decreasing that as well.
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Matthew Guthaus
05/28/2021, 4:30 PMcheck the setting..
just check the setting...
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Bhawandeep Singh Harsh
05/28/2021, 4:31 PMThanks, I am using these -
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set ::env(FP_CORE_UTIL) "40"
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
set ::env(PL_ROUTABILITY_DRIVEN) 1m
Matthew Guthaus
05/28/2021, 4:32 PMI don't know how to say it any other way. Check the setting of PL_BASIC_PLACEMENT
It may be set to the nondefaut value by the caravel scripts
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Bhawandeep Singh Harsh
05/28/2021, 4:39 PMThanks, I have another build going with it explicitly reset to 0.
Thanks, Prrof. @Matthew Guthaus . Its exactly same number of violations with PL_BASIC_PLACEMENT explicitly cleared to 0 also
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Matthew Guthaus
05/28/2021, 5:01 PMOk. Then you need to decrease the density some other way
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Bhawandeep Singh Harsh
05/28/2021, 5:03 PMThanks, I am triyng that next.
DRC violations increased by a couple thousand
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Matthew Guthaus
05/28/2021, 8:30 PMWhat does the placement look like now?
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Bhawandeep Singh Harsh
05/28/2021, 8:31 PMuser_project_wrapper.placement.def.png
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Matthew Guthaus
05/28/2021, 8:31 PMThat is still really dense and not spread out
it's no different than before?
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Bhawandeep Singh Harsh
05/28/2021, 8:32 PMPlacement is different, # of DRC violations is very slightly more
Let me try changing FP_CORE_UTIL and PL_TARGET_DENSITY futher
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Matthew Guthaus
05/28/2021, 8:52 PMThe placement is not very different
It is still roughly the same utilization
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Bhawandeep Singh Harsh
05/28/2021, 9:31 PMDecreasing FP_CORE_UTIL and PL_TARGET_DENSITY further increased DRC violations slightly
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Matthew Guthaus
05/28/2021, 9:35 PMwhy isn't it spreading it out more? your PL_TARGET_DENSITY is being ignored
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Bhawandeep Singh Harsh
05/28/2021, 9:40 PMThanks, a confirmation if I am doing it right. I am decreasing the FP_CORE_UTIL. PL_TARGET_DENSITY is in terms of FP_CORE_UTIL as -
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set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]m
Matthew Guthaus
05/28/2021, 9:51 PMIt still looks like PL_BASIC_PLACEMENT is true to me
shrug you will have to debug this.
Does it output anything about the density? Or the global routing?
You can also change the GLOBAL_RT_ADJUSTMENT
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Bhawandeep Singh Harsh
05/28/2021, 10:14 PMThanks, this is from the config.tcl dumped in the runs directory
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set ::env(PL_BASIC_PLACEMENT) "0"m
Matthew Guthaus
05/28/2021, 10:17 PMThat is probably setting it as a string
I'm not sure though. You'll need to learn to debug...
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Bhawandeep Singh Harsh
05/28/2021, 10:18 PMSure, thanks
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Matthew Guthaus
05/28/2021, 10:20 PMYes, every other example does:
set ::env(PL_BASIC_PLACEMENT) 0
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Bhawandeep Singh Harsh
05/28/2021, 10:22 PMI have done the same as well, given 0 without quotes. I think both with and without quotes work, I have not seen that make a difference for non-string values. My setting is -
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set ::env(PL_BASIC_PLACEMENT) 0m
Matthew Guthaus
05/28/2021, 10:23 PMHow else can you debug why it isn't spreading things out?
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Bhawandeep Singh Harsh
05/28/2021, 10:24 PMIs my understanding correct - I am decreasing the FP_CORE_UTIL. PL_TARGET_DENSITY is in terms of FP_CORE_UTIL as -
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set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]m
Matthew Guthaus
05/28/2021, 10:24 PMWhy do you think you would do that?
What is the purpose of that expr
(I'm not saying it's wrong, I'm asking why)
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Bhawandeep Singh Harsh
05/28/2021, 10:26 PMMy understanding is that decreasing FP_CORE_UTIL means logic cells will take less area, leaving more area for routing. DEcreasing PL_TARGET_DENSITY, will decrease density, making the layout sparse/ spread out and leaving more room for routing.
The expression I just took from example.
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Matthew Guthaus
05/28/2021, 10:27 PMFP_CORE_UTIL determines the floorplan utilization. It makes the floorplan bigger compared to the total cell area if you have a relative sized floorplan
PL_TARGET_DENSITY tells the placer how much local density should be in a given area. So it tries to spread the cells out more inside the area. It has to be bigger than FP_CORE_UTIL because even if everything is perfectly distributed, the best you could do is FP_CORE_UTIL for the local density everywhere
What happens in that expression now?
You are fixing them so that PL_TARGET_DENSITY is always percent more than the other
Is that a good number?
Does your log say anything during placement about density?
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Bhawandeep Singh Harsh
05/28/2021, 10:31 PMThe run log does not say anything about error or not, it just prints the value used, then the area and then the new value it calculated, that is very slightly more than actual value.
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Matthew Guthaus
05/28/2021, 10:34 PMWhat else can you try?
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Bhawandeep Singh Harsh
05/28/2021, 10:46 PMI have tried changing FP_CORE_UTIL, PL_TARGET_DENSITY, GLB_RT_ADJUSTMENT and PL_ROUTABILITY_DRIVEN.
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Matthew Guthaus
05/28/2021, 10:48 PMWhat ELSE can you try?
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Bhawandeep Singh Harsh
05/28/2021, 10:48 PMThe violation is -
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Local interconnect minimum area < 0.0561um^2 (li.6)m
Matthew Guthaus
05/28/2021, 10:48 PMWhere do you get that error?
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Bhawandeep Singh Harsh
05/28/2021, 10:48 PMI am checking all variables, if something sounds like it will impact this.
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Matthew Guthaus
05/28/2021, 10:48 PMIn the layout
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Bhawandeep Singh Harsh
05/28/2021, 10:49 PMThe flow completes, it says there are DRC violations.
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Matthew Guthaus
05/28/2021, 10:51 PMlook at the layout and see where the errors are
debug it
you can see why they happen
ok, i need to go for now
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Bhawandeep Singh Harsh
05/28/2021, 10:51 PMSure, thanks
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Hieu Bui
05/29/2021, 3:59 AMHi Bhawandeep, have you commit your config to your github? I can take a look at it.
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Bhawandeep Singh Harsh
05/29/2021, 3:59 AMI will do it now, thanks
Thanks a lot once again, pushed just now, the link is - https://github.com/bhawandeepsingh/darkriscv_in_openlane.
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Hieu Bui
05/29/2021, 4:17 AMThanks. I will take a look rightnow :)
I have run your script and I do not get any DRC problem. However, LVS failed.
Which version of the PDK and the openlane that you are using? I am using openlane v0.15 and the pdk commit from Caravel_lite and there are no DRC error. The LVS error might be of the power & ground net. there are 3 net different between the verilog netlist and the layout.
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Bhawandeep Singh Harsh
05/29/2021, 6:28 AMThanks, let me see the versions.
PDK version - 1.0.156
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Hieu Bui
05/29/2021, 6:33 AMyou can cd to 'openlane/user_project_wrapper/runs/user_project_wrapper' and run 'cat PDK_SOURCES' and 'cat OPENLANE_VERSION'
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Bhawandeep Singh Harsh
05/29/2021, 6:34 AMI do not see Openlane version anywhere in the OPenlane_root directory. The build log shows - Version: v0.15
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Hieu Bui
05/29/2021, 6:35 AMThese are mine:
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$ cat OPENLANE_VERSION
openlane v0.15
$ cat PDK_SOURCES
skywater-pdk bb2f842ac8d1b750677ca25bc71fb312859edb82
open_pdks 7e29496eecf3ee8e1766f1b7f9441f97204d4735b
Bhawandeep Singh Harsh
05/29/2021, 6:36 AMThanks, I get -
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$ cat OPENLANE_VERSION
openlane v0.15
$ cat PDK_SOURCES
-ne skywater-pdk
bb2f842ac8d1b750677ca25bc71fb312859edb82
-ne open_pdks
7e29496eecf3ee8e1766f1b7f9441f97204d4735h
Hieu Bui
05/29/2021, 6:37 AMI also think that you should harden the darksocv as a macro first, then assemble it into the user_project_wrapper because the user_project_wrapper are specific to Caravel test harness.
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Bhawandeep Singh Harsh
05/29/2021, 6:38 AMI will try that next, 1 question - I see -ne in my results above, but not in your results, any idea what that is and if that makes a difference
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Hieu Bui
05/29/2021, 6:39 AMFor that I have no idea. Are you using the tools from the docker image or you build the tool yourself?
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Bhawandeep Singh Harsh
05/29/2021, 6:42 AMI am using docker, but I am using docker first time, so highly likely I am doing something wrong there.
Are you using docker image or you build yourself ?
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Hieu Bui
05/29/2021, 7:17 AMI use the docker image from openlane
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Bhawandeep Singh Harsh
05/29/2021, 7:18 AMThanks, I have another question, even in my run it says no DRC violations after detailed routing and then no LVS mismatches. But after that I have violations in magic drc, Do you see no DRC violations in drc after detailed routing or in magic drc ?
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Hieu Bui
05/29/2021, 7:23 AMThere is no drc violation after detailed routing
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Bhawandeep Singh Harsh
05/29/2021, 7:26 AMOh, then there is a disconnect, in my run also, there are no drc violations after detailed routing, no lvs violations, but after that magic drc gives violations.
Thanks, for you did the flow reach completion without erroring out ? Were there only 3 lvs violations after flow completion ?
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Hieu Bui
05/29/2021, 7:29 AMThe flow does not complete. It stops at the lvs error.
Maybe you can try with a clean version of the tools and PDK. checkout your github project to a new folder and then install openlane and pdk as explained in the document.
You can also try to run the default caravel_user_project to see if there is any problem with the pdk and the tool. It should work.
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Bhawandeep Singh Harsh
05/29/2021, 8:15 AMI have drc violations in user_project_example also. Something about tools is probably messed up
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Hieu Bui
05/29/2021, 10:00 AMHow do you open the project in Magic?
Did you build the pdk by running "make pdk-nonnative"?
In your setup, you should add your account to docker group and remove this line:
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sudo chmod 666 /var/run/docker.sock Copy code
$ gpasswd -a <your account> dockerAlso, I do not use the full Caravel test harness. Caravel Lite is good enough for me.
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Bhawandeep Singh Harsh
05/29/2021, 10:55 AMI do not open the project in magic, the step is run as part of
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make <project> Copy code
make pdka
ALI AHMED
06/03/2021, 8:22 PM@Aireen Amir Jalal please read the thread, may be helpful with the versions and caravel integration.
👀 1
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Aireen Amir Jalal
06/04/2021, 5:51 AMSure Sir @ALI AHMED!