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Amogh Lonkar
05/30/2021, 11:17 PMWhat causes MetSpc routing violations and what is the best way to fix those? Getting
Copy code
violation type: MetSpc
srcs: repeater1/OBS wb_clk_i
bbox = ( 71.34, 137.105 ) - ( 71.445, 137.275 ) on Layer li1m
Matthew Guthaus
05/30/2021, 11:20 PMRouting issues are likely due to congestion. What does your placement look like?
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Amogh Lonkar
05/30/2021, 11:24 PMCapture.PNG
perhaps reducing placement density would help?
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Matthew Guthaus
05/30/2021, 11:31 PMI can't really see the placement. Is that a macro block that you created ?
Rather than making a macro that gets placed in user_project_wrapper, I would recommend putting your design directly in user_project_wrapper
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Amogh Lonkar
05/30/2021, 11:32 PMdidn't create any macro blocks
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Matthew Guthaus
05/30/2021, 11:32 PMwhat is that then? is that openram_testchip?
according to your repo, you are making a macro called openram_testchp that I assume will get placed in user_project_wrapper?
(or at least there is an openlane/openram_testchip/config.tcl...)
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Amogh Lonkar
05/30/2021, 11:33 PMI had created initially, but I'm not using it since the logic will be in the top level
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Matthew Guthaus
05/30/2021, 11:34 PMAh, ok, delete that to make it less confusing then 🙂
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Amogh Lonkar
05/30/2021, 11:34 PMthe result I sent was from klayout in the runs/results/floorplan
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Matthew Guthaus
05/30/2021, 11:34 PMfrom user_project_wrapper?
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Amogh Lonkar
05/30/2021, 11:34 PMyes
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Matthew Guthaus
05/30/2021, 11:35 PMThe png files are a bit hard to see sometimes, so I recommend viewing them in magic:
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lef read merged_padded.lef
def read user_project_wrapper.def👍 1
(from that directory since there should be a .magicrc to set up the technology in there)
If congestion is a problem, you can set PL_TARGET_DENSITY to spread the cells out more. You can also adjust GLB_RT_ADJUSTMENT to reserve more global wires which can cause routing to spread out.
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Manar Abdelatty
05/31/2021, 6:33 PM@Amogh Lonkar I have seen this before when CTS inserts one of the cells that are part of the drc exclude list (https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/sky130_fd_sc_hd/drc_exclude.cells). Do you have any of those in your def file, especially
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1a
Amogh Lonkar
05/31/2021, 6:44 PMNone of the exluded cells seem to be in the placement def file
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Manar Abdelatty
05/31/2021, 6:54 PM@Amogh Lonkar You can check where the violation is happening exactly by loading the def file in klayout from File -> import -> DEF/LEF. Then under
import fileWith LEF filesmerged.lef<run-dir>/tmp/merged.lef71.34, 137.105a
Amogh Lonkar
05/31/2021, 6:55 PMI will try that, thank you!
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Matthew Guthaus
05/31/2021, 7:37 PM@Manar Abdelatty I've never been able to get klayout to open the lef cells. I actually filed a bug and it was recently fixed in the newest klayout. What version were you using that that worked?
@Amogh Lonkar you can also do this in magic if that doesn't work:
lef read merged.lef
def read file.def
drc find
(must be in a directory with a .magicrc for the technology)
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Amogh Lonkar
05/31/2021, 7:46 PMfrom the klayout view, it just seems to be pointing to a wire/pin but hard to determine what the is causing the problem.
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Manar Abdelatty
05/31/2021, 7:47 PM@Matthew Guthaus Mine is
KLayout 0.26.9a
Amogh Lonkar
05/31/2021, 7:48 PM@Matthew Guthaus my magic has some issues reading the lef and def files and adding the sky130A.magicrc was causing segfaults and killing magic.
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Matthew Guthaus
05/31/2021, 8:14 PM@Amogh Lonkar make sure you have a recent version. If it comes in a package it is probably too old
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Manar Abdelatty
06/01/2021, 9:54 AM@Amogh Lonkar Is it flagged inside a cell ? You can also try to slightly increase the
GLB_RT_ADJUSTMENTa
Amogh Lonkar
06/01/2021, 3:10 PMI can try doing that. There aren't any standard cells placed there and I've set macros to be placed at fixed position 75(violation occurs at 71) and can't see those being placed in klayout even though the placement def file says they've been placed.
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Manar Abdelatty
06/01/2021, 3:13 PM@Amogh Lonkar Probably you didn't load the LEF file (merged.lef) when you imported the def file
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Amogh Lonkar
06/01/2021, 3:14 PMjust double checked, did import both
Basic question, but this is how it should be right?
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Manar Abdelatty
06/01/2021, 3:18 PM@Amogh Lonkar Yes that is right. It could be the same issue that @Matthew Guthaus pointed out with loading the LEF file in klayout
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Amogh Lonkar
06/01/2021, 3:20 PMweirdly, we were able to see macros in klayout in a smaller intermediate design we were testing which failed because of the same violations
Once my magic is updated, I'll check in that
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Matthew Guthaus
06/01/2021, 3:30 PMYou'll see lines through the cell names in the cell pane if they aren't loaded
@Amogh Lonkar are you sure you didn't see routing and power? I've never gotten the LEF to load
It's literally a bug that was fixed
https://github.com/KLayout/klayout/issues/777
It's only when the LEF cells have a "foreign" statement which means it is looking for the gds instead of the lef
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Amogh Lonkar
06/01/2021, 3:40 PMNot sure what it was then, I was looking at it on Jesse's screen and we saw two smallish squares blocked on the bottom left. We assumed they were the sram macros since the position seemed correct
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Matthew Guthaus
06/01/2021, 3:52 PMIf the SRAM macros don't have a foreign statement, it'll work. I think I removed it in OpenRAM
The standard cells have it, however
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Amogh Lonkar
06/01/2021, 8:15 PMIt looks like a standard cell is being placed on a metal layer. Is there a way to define where std cells can be placed?
In general, it seems like the top level std cells are being placed all over instead of closer to the macros.
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Matthew Guthaus
06/01/2021, 8:21 PM@Amogh Lonkar I don't think that is a standard cell. You need to expand the view to view all levels of hierarchy. Click outside the area, press "s" to select everything, type "x" to expand all
It could be an antenna diode or somethign
It's in the halo so it is definitely not a standard cell. Not sure what it is
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Amogh Lonkar
06/01/2021, 8:29 PMlabel says sky130_fd_sc_hd_comb_1 #1529
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Matthew Guthaus
06/01/2021, 9:24 PMWhat cell is that?
Also, is that really a problem? That is metal5 over the cell right? There should be M1-M4 to route on
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Amogh Lonkar
06/01/2021, 9:28 PMthose are the coordinates of the violation, not sure if that exact cell is the problem. There isn't anything else there to cause an issue.
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Matthew Guthaus
06/01/2021, 11:30 PMI mean, it's a valid cell, so that alone isn't an error. You can iterate through the errors in magic with "drc find"
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Amogh Lonkar
06/01/2021, 11:31 PMthere aren't any drc violations
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Matthew Guthaus
06/01/2021, 11:36 PMWhere is that error message from?
Can you share the design?
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Amogh Lonkar
06/01/2021, 11:36 PMit comes from reports/routing/21-triton.drc
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Matthew Guthaus
06/01/2021, 11:39 PMwhat layout are you viewing?
are you viewing the input to the router?
Or do you see routes?
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Amogh Lonkar
06/01/2021, 11:42 PMI can see the routes
there's a repeater touching the SRAM macro, but still no drc violations from
drc findm
Matthew Guthaus
06/02/2021, 12:11 AMCan you share the design somehow?
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Amogh Lonkar
06/02/2021, 12:12 AMFinishing up a run, I'll share the def/lef files
I think my macro placement might be the issue, still getting the same error but still need to increase the gap with the repeater
Has nothing to do with the macro, it is the repeater insertion causing the problem.
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Manar Abdelatty
06/02/2021, 10:28 AM@Amogh Lonkar You have one of the cells that are part of the drc exclude list in the def file design
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1👍 1
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Amogh Lonkar
06/02/2021, 3:09 PMThank you!
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ALI AHMED
06/04/2021, 4:20 PM@Rameen Anwar
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