1. You can use yosys to read your verilog and give you a netlist. I don't know if it's possible to get non flattened after synthesis to the standard cells. Look at the synth.tcl script in openlane for details on the commands used.

1. Yes there is a variable named (SYNTH_NO FLAT) 2. Its not the area, I have increased it to about 4 times but the same error. I don't think target density would have a role in it since the error occurs at

run_floorplan

, before

placement