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#openlane
Title
# openlane
m

Matt Venn

05/31/2021, 6:01 PM
1. You can use yosys to read your verilog and give you a netlist. I don't know if it's possible to get non flattened after synthesis to the standard cells. Look at the synth.tcl script in openlane for details on the commands used.
w

Wajeh ul hasan

06/01/2021, 6:15 AM
1. Yes there is a variable named (SYNTH_NO FLAT) 2. Its not the area, I have increased it to about 4 times but the same error. I don't think target density would have a role in it since the error occurs at
run_floorplan
, before
placement