Hi I ve been trying to generate pdn for my design using gen

Question

Hi I ve been trying to generate pdn for my design using gen pdn command but it has been stuck here since the past 2 5 hours Has anyone else faced a similar issue

Aireen Amir Jalal · Answer

One important thing here is that I ve used a netlist generated through Genus as we have our rtl in systemverilog I am using openlane for steps floorplan onwards

Manar Abdelatty · Answer

< Aireen Amir Jalal> Yes the current solution is to disable this check by setting `FP PDN CHECK NODES` to 0

Aireen Amir Jalal · Answer

Thanks < Manar Abdelatty> this setting worked out I am now facing a similar issue at detailed placement or step It s been stuck here for a while now Any settings for this case too

Aireen Amir Jalal · Answer

Nevermind it completed Thanks

Aireen Amir Jalal · Answer

Hi < Manar Abdelatty> I am currently on the cts stage and its been almost 10 hours but the flow is stuck at this stage Am I missing some important parameter setting here

Manar Abdelatty · Answer

< Aireen Amir Jalal> I amn t completely sure but it could be stuck at the resizer stage due the high `wns` you can increase the clock period to address the negative slack

Aireen Amir Jalal · Answer

< Manar Abdelatty> I tried setting this variable `CTS REPORT TIMING 0` and it went past this stage

Aireen Amir Jalal · Answer

Sure i ll try it with increased clock period as well Thanks

Aireen Amir Jalal · Answer

< Manar Abdelatty> Any leads on how to solve this global route issue

Manar Abdelatty · Answer

< Aireen Amir Jalal> I would try changing the `PL TARGET DENSITY` or `GLB RT ADJUSTMENT`

Aireen Amir Jalal · Answer

What values would you suggest I ve tried ranging `GLB RT ADJUSTMENT` from 0 3 0 55 and `PL TARGET DENSITY` to 0 7 but the error still persists

Aireen Amir Jalal · Answer

< Manar Abdelatty> can you please point out the possible reason for this log error at place io step