https://open-source-silicon.dev logo
m

Matt Venn

06/01/2021, 3:27 PM
take a look a the lvs.lef.log - should make it obvious which pins are missing
y

Yuanpeng Liao

06/01/2021, 4:05 PM
Thank you. I checked this file and it shows power nets are missing in circuit 2. I need to change config.tcl
m

Matt Venn

06/01/2021, 4:06 PM
have you included the power rails in the config.tcl for your design as in the example user_proj_example?
y

Yuanpeng Liao

06/01/2021, 4:11 PM
Yes I did. But it is not consistent as the power net in the wrapper.
m

Manar Abdelatty

06/02/2021, 10:49 AM
@Yuanpeng Liao I think the power pins of the subservient aren't connected from the top level. You can check this by viewing the layout in klayout and making sure that at least 8 metal 5 straps overlap with the macro.