I am trying to add DFFRAM from the the efabless caravel system to my own design but I am getting this error. 8.3. Executing AST frontend in derive mode using pre-parsed AST for module `\DFFRAM'. ERROR: Module `\sky130_fd_sc_hd__clkbuf_4' referenced in module `\DFFRAM' in cell `\DOBUF[31]' is not part of the design. How do I add the reference to the cell? Any assistance would be appreciated..

Have you been able to run the tests? It looks like a toolchain fail

Yes run the tests. Then placed the rtl for the riscv core that I am deploying. Then deployed two of the cores as macros, that was ok. This is the first time I have rtl that references one of the skywater cells directly.

You're not trying to put logic in user project wrapper are you?

I just use project_wrapper for macro placement. At the moment I am in user_proj_example trying to add https://github.com/efabless/caravel/blob/master/verilog/rtl/DFFRAM.v it seems the compiler is just not finding a reference to sky130_fd_sc_hd__clk_buf_4.

No idea

@Matt Venn thanks for looking and kudos on the zero to asic work.

Good to know