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#openlane
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# openlane
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Andy Attwood

06/11/2021, 3:26 PM
I am trying to add DFFRAM from the the efabless caravel system to my own design but I am getting this error. 8.3. Executing AST frontend in derive mode using pre-parsed AST for module `\DFFRAM'. ERROR: Module `\sky130_fd_sc_hd__clkbuf_4' referenced in module `\DFFRAM' in cell `\DOBUF[31]' is not part of the design. How do I add the reference to the cell? Any assistance would be appreciated..
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Matt Venn

06/11/2021, 4:50 PM
Have you been able to run the tests? It looks like a toolchain fail
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Andy Attwood

06/11/2021, 5:33 PM
Yes run the tests. Then placed the rtl for the riscv core that I am deploying. Then deployed two of the cores as macros, that was ok. This is the first time I have rtl that references one of the skywater cells directly.
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Matt Venn

06/11/2021, 5:38 PM
You're not trying to put logic in user project wrapper are you?
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Andy Attwood

06/11/2021, 6:05 PM
I just use project_wrapper for macro placement. At the moment I am in user_proj_example trying to add https://github.com/efabless/caravel/blob/master/verilog/rtl/DFFRAM.v it seems the compiler is just not finding a reference to sky130_fd_sc_hd__clk_buf_4.
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Matt Venn

06/11/2021, 6:10 PM
No idea
Maybe @Tim Edwards could shine some light
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Andy Attwood

06/11/2021, 6:14 PM
@Matt Venn thanks for looking and kudos on the zero to asic work.
👍 1
This fixed the issue set ::env(LIB_SYNTH) [glob /disk2/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_100C_1v80.lib]
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Matt Venn

06/12/2021, 5:01 AM
Good to know