Hello, I encountered a problem when reading a Systemverilog package with Yosys. Error message is as shown below: [2:14 PM] 2. Executing Verilog-2005 frontend: ./designs/src/opentitan_soc/ip/prim/rtl/prim_util_pkg.sv ./designs/src/opentitan_soc/ip/prim/rtl/prim_util_pkg.sv37 ERROR: syntax error, unexpected TOK_ID make: * [results/sky130hd/opentitan_soc/base/1_1_yosys.v] Error 1 [2:15 PM] and the corresponding code is as followed  28   function automatic integer _clog2(integer value);  29     integer result;  30     // Use an intermediate value to avoid assigning to an input port, which produces a warning in  31     // Synopsys DC.  32     integer v = value;  33     v = v - 1;  34     for (result = 0; v > 0; result++) begin  35       v = v >> 1;  36     end  37     return result;  38   endfunction [2:15 PM] So newest version of yosys might not support "return", or we might do something wrong?

Sv not supported in the open source version

OK, thanks!

@Peijun Hou I take my sv through this tool https://github.com/zachjs/sv2v

Yes! and the tool give me some error: $ sv2v --write=adjacent prim_util_pkg.sv Warning: Source includes packages but no modules. Please convert packages alongside the modules that use them. And the verilog is as follows: package prim_util_pkg;   function automatic integer _clog2(integer value);     integer result;     integer v = value;     v = v - 1;     for (result = 0; v > 0; result++) begin       v = v >> 1;     end     return result;   endfunction   function automatic integer vbits(integer value); `ifdef XCELIUM     return (value == 1) ? 1 : _clog2(value); `else     return (value == 1) ? 1 : $clog2(value); `endif   endfunction endpackage

@Peijun Hou please file a github issue