open-source-silicon.dev

Has anyone experimented with the `zinit` pass in yosys?

hi <@U017REC9K36> I'm not familiar with this option but after reading the doc page (<http://www.clifford.at/yosys/cmd_zinit.html>) it would appear it ensure that all FFs (flip flops) in a design are initialized to 0 whether or not you have done so in the RTL

This would ensure there is no unknown start-up state. IIRC, at least for Xilinx FPGAs, FFs come up with a 0 unless you have set them otherwise

Of course with ASICs, there are no default values unless you code it as such, but this option may make that easier.

Right, so this seems like something more FPGA-oriented. AFAIK Yosys wouldn't have a way of doing this for FF on ASIC since it doesn't know the reset?

The context of this is I am looking to flag any uninitialized registers. Right now I do syntax level checks, but these are brittle. We are developing for both FPGA and ASIC so trying to avoid regressions on the ASIC side of things.

My instinct is that `zinit` won't help here for ASIC flows.

Just thinking out loud... besides there probably being a commercial tool to do this what if you made a simple testbench that only asserts and then deasserts reset. If all signals were dumped to a vcd file you could parse it for signals that show X? That's a pretty nasty hack though

Regarding zinit, I think you're correct in that it will not flag uninitialized registers, but it seems like it will ensure they are initialized. I would suggest reaching out to Claire and see what her opinions are on that option in an FPGA vs ASIC environment

<@U017REC9K36> You are right about zinit and ASIC. In ASIC flipflops can only be given a known state by either clocking it or by a reset/set assertion. The value after power-up is random 0 or 1.
Actually for ASIC one would need to initialize all flipflops to unknown state to match reallity.

<@U0177MGKM7A> IIUC one can model that behavior with a gate level synthesis. <@U018F616ZTL> I like the idea of VCD parse and dump (on a GL sim), since it should give the full symbol table with the proper simulation flags.

Though, It seems something like this you need AST access to do two checks. One if the value is initialized, and the second if it is initialized on reset. It sounds like the "proper"way to do this is in Yosys somewhere, before name mangling occurs, etc. Maybe there are formal verification approaches as well? Anyway, I'll keep noodling a bit. Thanks for the help guys!

<@U017REC9K36> I use mainly cocotb for testbench definition and simulation. What I have done in the past is initialize all registers with a random 0 or 1. After synthesis you should be able to do this by using the cell name (e.g. all the flipflops).
I did not use 'U' or 'X' because of the X-poisoning problem. I had a JTAG interface in my design and that has a state machine that can be reset by providing it a number of ones on the input for a few clocks. Post-synthesis the flops of this state machine stayed X as the simulation could not derive anymore that it would evolve to a known state after this specific input.