Hi, I'm trying to launch the gate level simulation...
# openlane
Hi, I'm trying to launch the gate level simulation, but I get this error from caravel.
Copy code
caravel/verilog/gl/caravel.v:3483: error: port ``la_oen'' is not a port of mprj.
I look the user project wrapper and that signal does not exist, I found a similar signal call la_oenb. Is the same signal? is an error in caravel or an error from my code?
I am getting the same error
GL has been broken for caravel for a long time. I would suggest running caravel as normal, but substituting just your design's GL
This may be obvious to many people, but often 'b' is appended to a signal to mean the 'bar' or inverse of a signal. 'bar' comes from boolean arithmetic where a line or 'bar' drawn over a variable represents the opposite logic value. tl;dr
is most likely intended to be the inverse of
yeah, the names were updated in the verilog but the gate level has never been updated
also it's missing the IRQs
@Matt Venn How I suppose to the only test the GL of my code ? what I need to change to make that happen?