I have not really used the openlane flow yet but I assume it

Question

I have not really used the openlane flow yet but I assume it would be possible to generate a new lef file or whatever tells the pnr tool where to route things that excludes the areas containing my analog design and then just have it route inside that

Hieu Bui · Answer

Openlane is quite straightforward You just need the right configuration You can make your design as a macro and Openlane openroad can place it and connect it to the IOs However we are currently facing the issue with the lef generation Some versions of our macro with the lef generated by Magic can t be route with TritonRoute I don t know if others face this problem

Weston Braun · Answer

I sorta have the inverse problem I have an already routed chip and want to route a digital design in the remaining areas IOs

Hieu Bui · Answer

I think that you can use openlane to generate the layout for the digital module and then put it in your chip

Matt Venn · Answer

Maybe you can team up with < Amro Tork> He needs a bit of space a d has openlane experience

Amro Tork · Answer

Hi < Hieu Bui>

Amro Tork · Answer

I have space

Amro Tork · Answer

But have constraints on pins

Amro Tork · Answer

How many pins

Amro Tork · Answer

Or we could use < Matt Venn> multi project to create a new multi project

Amro Tork · Answer

< Matt Venn> Could you advise how to use this multi project repo

Amro Tork · Answer

I can wrap a new multi project just like yours

Hieu Bui · Answer

Hi Amro Tork I am trying to finish our project It can pass precheck already and it is quite big with two 4k SRAMs However we got something very weird when integrating a customized cell into openlane

Weston Braun · Answer

One of my friends < Peter Schmidt Nielsen> was hoping to put something on the extra space and already has something that routes but we dont know how to create a custom wrapper to have it route in instead of the whole chip area

Amro Tork · Answer

< Weston Braun> Is yours Analog

Weston Braun · Answer

yah

Amro Tork · Answer

< Hieu Bui> How big is your design Dimensions

Weston Braun · Answer

I used all the pins

Amro Tork · Answer

But you have the digital pins free

Weston Braun · Answer

Is there a way to disable to wishbone bus from the management processor Or can a bad design on the bus lock the chip

Amro Tork · Answer

Not sure about that

Matt Venn · Answer

Only writes to 0x30 will get passed thru

Weston Braun · Answer

The only constraint here is that I cant risk the rest of the functionality

Matt Venn · Answer

So ignore it

Weston Braun · Answer

So there is no way that a bad design on the digital lines can lock the chip

Matt Venn · Answer

< Amro Tork> the multi tools are fairly well documented now and there are lots of example sub projects

Weston Braun · Answer

this is my layout

Weston Braun · Answer

I would need to route the power from one of the 1V8 pins for you

Weston Braun · Answer

I am using none of the digital IO

Amro Tork · Answer

Could I place my osc with you

Amro Tork · Answer

< Weston Braun>

Amro Tork · Answer

Digital only

Amro Tork · Answer

< Matt Venn> thanks I ll take a look at it now

Weston Braun · Answer

If you can figure out a way to route a drc clean design that does not overlap with any of my chip area I assume we can OR the two designs together or something

Matt Venn · Answer

What do you mean lock the chip

Amro Tork · Answer

< Weston Braun> yes I can

Weston Braun · Answer

I need the management core to configure the IO states If a bad digital design locks up the managment core I will be very sad

Amro Tork · Answer

Where is your repo

Amro Tork · Answer

Did you do fill

Weston Braun · Answer

Stanford secured tapeout slots through the Chipignite program so this is actually taping out So adding a digital design is basically all risk no reward for me

Weston Braun · Answer

they do the fill after submission no This passes the local prechecks but not the online one because that uses an outdated magic version

Amro Tork · Answer

Cool

Amro Tork · Answer

< Weston Braun> no worries

Weston Braun · Answer

I need to integrate one last thing connecting to the last IO So just assume constant clearance from the edges And I need to route a power rail for you from the external 1V8 pin

Weston Braun · Answer

Also if you figure this out you need to help < Peter Schmidt Nielsen> get his design into the digital logic area too I assume your design is small ish His is too

Weston Braun · Answer

He only needs the LA bus

Weston Braun · Answer

and not all the pins

Matt Venn · Answer

I can t think of any way that could happen

Weston Braun · Answer

I can ask Tim Edwards tommor

Weston Braun · Answer

A tapeout is like 10k or whatever I dont want to screw it up

Amro Tork · Answer

Tell < Peter Schmidt Nielsen> to contact me

Weston Braun · Answer

repo is here <https github com westonb Open PMIC tapeout>

Amro Tork · Answer

Oh

Amro Tork · Answer

Is that an LDO

Weston Braun · Answer

its a current mode buck converter

Amro Tork · Answer

What s your output voltage

Amro Tork · Answer

1 8

Weston Braun · Answer

1 8V

Weston Braun · Answer

I also lowkey want some digital logic on the chip because then I can power it from the buck converter

Amro Tork · Answer

Did you pass corners

Amro Tork · Answer

And everything

Weston Braun · Answer

I am having extraction issues for parasitics but the initial design passes all process and load corner cases

Amro Tork · Answer

Nice

Amro Tork · Answer

Glad to see that rolling

Amro Tork · Answer

Are you sharing the design spice and schematics

Weston Braun · Answer

Yah the repo is a mess right now

Weston Braun · Answer

I am migrating everything over but its all FOSS

Amro Tork · Answer

Nice

Amro Tork · Answer

Thanks Weston

Peter Schmidt-Nielsen · Answer

< Amro Tork> Hello yes I d love to get some help on this

Amro Tork · Answer

HI < Peter Schmidt Nielsen>

Peter Schmidt-Nielsen · Answer

I have some Verilog and I assume it s relatively synthesizable I only ever `always posedge clock ` never use ` ` or `initial` and whatnot so I assume it should be able to synthesize a single big block of combinational logic and set of registers and that s it but I haven t been able to synthesize it with the `caravel user project` stuff for silly reasons

Amro Tork · Answer

Is yours analog or digital

Peter Schmidt-Nielsen · Answer

Completely digital

Amro Tork · Answer

Great

Amro Tork · Answer

I need the GDS from Openlane not form caravel user project

Amro Tork · Answer

I m not able to Synthesize from caravel user project as well

Amro Tork · Answer

Ignore it for now

Peter Schmidt-Nielsen · Answer

Aha got it

Peter Schmidt-Nielsen · Answer

How have you been building said GDS I d be happy to try to build it I can also put my Verilog up somewhere

Peter Schmidt-Nielsen · Answer

I ve just been doing `make user project wrapper` and `make user proj example`

Amro Tork · Answer

< Peter Schmidt Nielsen> You need to use Openlane RTL to GDS flow

Amro Tork · Answer

Assuming that your Verilog is RTL

Peter Schmidt-Nielsen · Answer

Okay got it I think I have all the openlane and PDK stuff installed although I don t know how to invoke it directly I can launch into trying to do this right now

Peter Schmidt-Nielsen · Answer

By your Verilog is RTL you mean I never request FETs or gates and stuff and only ever ` lt =` into registers

Amro Tork · Answer

I don t think you go to FETs

Amro Tork · Answer

Very rarely Gates

Peter Schmidt-Nielsen · Answer

If so yes 100 of what I ve got is various ` lt =`s inside of `case`s `if`s in `always posedge clock ` blocks If I were manually implementing this I d just have a single big combinational block and a bunch of flip flops and that s it That s all I want it to synthesize

Amro Tork · Answer

Here is the steps for openlane in nutshell

Amro Tork · Answer

1 Clone openlane latest version 2 cd openlane 3 make openlane 4 make pdk 5 make test 6 create a new folder under designs with your design name peter chip for example 7 Copy one of the config tcl from one of the other designs in the designs folder to yours 8 Modify the config tcl as needed You will need to read openlane documentation for that 9 Copy your verilog into the your peter chip folder 10 make mount 11 flow tcl design peter chip tag first run

Amro Tork · Answer

Hopefully after all of that you don t get any errors through the process

Peter Schmidt-Nielsen · Answer

Okay sweet let me try that literally right now

Peter Schmidt-Nielsen · Answer

< Amro Tork> Okay this is working great for me what you suggested synthesized my design and spat out a GDS file As a next step do you know how I might be able to integrate this with what Weston has In particular I just need to get power clock and a handful of the logic analyzer lines Do I need to make a custom LEF for that

Peter Schmidt-Nielsen · Answer

I got this sort of thing out and a GDS file I have no idea where it hooked up the ports for my module I presume I need to separately specify where I need that to go I have no idea how to hook that up with the Caravel harness RISC V core and how to integrate that with Weston s GDS file

Peter Schmidt-Nielsen · Answer

I m currently looking at the LEF files that come with `caravel user project` they seem promising although I don t know how to make openlane route to them and I especially don t know how to make it not do anything in Weston s area

Matt Venn · Answer

after you have the separate hardened macros in gds and lef then you can instantiate and wire them up in user project wrapper

Matt Venn · Answer

then you choose where they are put in openlane user project wrapper macro cfg to set x and y

Matt Venn · Answer

then you run make user project wrapper and it will try to do the routing and PDN

Peter Schmidt-Nielsen · Answer

< Matt Venn> Got it thanks Are the GDS file and LEF file that I got by default via ` flow tcl design mything tag run1` in `designs snproc runs run1 results magic mything gds` and `designs snproc runs run1 results magic mything lef` the hardened macro to which you refer

Matt Venn · Answer

yes

Matt Venn · Answer

so those go in the top level gds and lef directories

Matt Venn · Answer

then look at how the wrapper instances mprj and replace that with your macro

Peter Schmidt-Nielsen · Answer

Okay sweet thanks so much I m going to check this out right now I ll probably have a bunch of questions

Peter Schmidt-Nielsen · Answer

< Matt Venn> Okay very cool I see in that `macro cfg` file you mention it gives x and y and sure enough those seem to be exactly where the user project was placed in `openlane user project wrapper runs user project wrapper results magic user project wrapper gds` I put the ` lef` and ` gds` into the top level `lef ` and `gds ` directories you mentioned I m trying to swap the entry in `macro cfg` out for my macro but the Python script is saying `AssertionError Macros not found snproc 1175000 1690000 N ` I tried adding my lef and gds files explicitly in the `config tcl` under `EXTRA LEFS` and `EXTRA GDS FILES` but to no avail

Peter Schmidt-Nielsen · Answer

Am I missing something super simple

Matt Venn · Answer

Have you instantiated it in user project wrapper

Peter Schmidt-Nielsen · Answer

I suspect not but I m not sure how Do you mean adding something to `verilog rtl user project wrapper v` Right now I see `user proj example mprj ` there at the end am I adding something comparable but that matches up with the defined pins in the ` lef` file I generated

Peter Schmidt-Nielsen · Answer

< Matt Venn> I m still unsure of how merging this with Weston s stuff will eventually work Like if I get the `user project wrapper` producing a GDS file with my stuff nicely routed to the various project wrapper pins I assume it ll still want to fill the entire space and thus won t be immediately mergable with Weston s GDS file Do you have thoughts on this Nope is of course a totally fine answer

Peter Schmidt-Nielsen · Answer

< Amro Tork> Do you know how to get power and clock signals into the block I synthesized I think I m pretty much ready with what I want to merge into Weston s GDS Were you also going to merge something in

Amro Tork · Answer

< Peter Schmidt Nielsen> I m not an expert on Openlane