Weston Braun
06/17/2021, 3:05 AMHieu Bui
06/17/2021, 3:43 AMWeston Braun
06/17/2021, 3:51 AMHieu Bui
06/17/2021, 3:55 AMMatt Venn
06/17/2021, 6:20 AMAmro Tork
06/17/2021, 6:24 AMHieu Bui
06/17/2021, 6:28 AMWeston Braun
06/17/2021, 6:29 AMAmro Tork
06/17/2021, 6:29 AMWeston Braun
06/17/2021, 6:30 AMAmro Tork
06/17/2021, 6:30 AMWeston Braun
06/17/2021, 6:30 AMAmro Tork
06/17/2021, 6:31 AMWeston Braun
06/17/2021, 6:31 AMAmro Tork
06/17/2021, 6:31 AMMatt Venn
06/17/2021, 6:32 AMWeston Braun
06/17/2021, 6:32 AMMatt Venn
06/17/2021, 6:32 AMWeston Braun
06/17/2021, 6:32 AMMatt Venn
06/17/2021, 6:32 AMWeston Braun
06/17/2021, 6:33 AMAmro Tork
06/17/2021, 6:33 AMWeston Braun
06/17/2021, 6:35 AMMatt Venn
06/17/2021, 6:35 AMAmro Tork
06/17/2021, 6:35 AMWeston Braun
06/17/2021, 6:35 AMAmro Tork
06/17/2021, 6:36 AMWeston Braun
06/17/2021, 6:36 AMAmro Tork
06/17/2021, 6:37 AMWeston Braun
06/17/2021, 6:38 AMMatt Venn
06/17/2021, 6:39 AMWeston Braun
06/17/2021, 6:39 AMAmro Tork
06/17/2021, 6:39 AMWeston Braun
06/17/2021, 6:39 AMAmro Tork
06/17/2021, 6:40 AMWeston Braun
06/17/2021, 6:40 AMAmro Tork
06/17/2021, 6:41 AMWeston Braun
06/17/2021, 6:42 AMAmro Tork
06/17/2021, 6:42 AMWeston Braun
06/17/2021, 6:42 AMAmro Tork
06/17/2021, 6:43 AMWeston Braun
06/17/2021, 6:44 AMAmro Tork
06/17/2021, 6:44 AMPeter Schmidt-Nielsen
06/17/2021, 6:53 AMAmro Tork
06/17/2021, 6:56 AMPeter Schmidt-Nielsen
06/17/2021, 6:56 AMalways @(posedge clock)
, never use #
, or initial
, and whatnot, so I assume it should be able to synthesize a single big block of combinational logic and set of registers and that's it.) but I haven't been able to synthesize it with the caravel_user_project
stuff for silly reasons.Amro Tork
06/17/2021, 6:56 AMPeter Schmidt-Nielsen
06/17/2021, 6:56 AMAmro Tork
06/17/2021, 6:56 AMPeter Schmidt-Nielsen
06/17/2021, 6:57 AMmake user_project_wrapper
and make user_proj_example
.Amro Tork
06/17/2021, 6:59 AMPeter Schmidt-Nielsen
06/17/2021, 7:00 AM<=
into registers?Amro Tork
06/17/2021, 7:01 AMPeter Schmidt-Nielsen
06/17/2021, 7:01 AMalways @(posedge clock)
blocks. If I were manually implementing this I'd just have a single big combinational block and a bunch of flip flops, and that's it. That's all I want it to synthesize.Amro Tork
06/17/2021, 7:02 AMPeter Schmidt-Nielsen
06/17/2021, 7:09 AMcaravel_user_project
, they seem promising, although I don't know how to make openlane route to them, and I especially don't know how to make it not do anything in Weston's area.Matt Venn
06/17/2021, 12:06 PMPeter Schmidt-Nielsen
06/17/2021, 6:31 PM./flow.tcl -design mything -tag run1
in designs/snproc/runs/run1/results/magic/mything.gds
and designs/snproc/runs/run1/results/magic/mything.lef
the hardened macro to which you refer?Matt Venn
06/17/2021, 6:31 PMPeter Schmidt-Nielsen
06/17/2021, 6:33 PMmacro.cfg
file you mention it gives x and y, and sure enough, those seem to be exactly where the user project was placed in openlane/user_project_wrapper/runs/user_project_wrapper/results/magic/user_project_wrapper.gds
. I put the .lef
and .gds
into the top-level lef/
and gds/
directories you mentioned. I'm trying to swap the entry in macro.cfg
out for my macro, but the Python script is saying AssertionError: ('Macros not found:', {'snproc': ['1175000', '1690000', 'N']})
. I tried adding my lef and gds files explicitly in the config.tcl
under EXTRA_LEFS
and EXTRA_GDS_FILES
, but to no avail.Matt Venn
06/17/2021, 7:24 PMPeter Schmidt-Nielsen
06/17/2021, 8:06 PMverilog/rtl/user_project_wrapper.v
? Right now I see user_proj_example mprj ( ... );
there at the end, am I adding something comparable, but that matches up with the defined pins in the .lef
file I generated?user_project_wrapper
producing a GDS file with my stuff nicely routed to the various project wrapper pins I assume it'll still want to fill the entire space, and thus won't be immediately mergable with Weston's GDS file. Do you have thoughts on this? "Nope" is, of course, a totally fine answer.Amro Tork
06/18/2021, 4:17 PM