Its sorta last minute before the tapeout, but I am...
# openlanew
Weston Braun
06/17/2021, 3:06 AMIts sorta last minute before the tapeout, but I am trying to to have ~ 5 mm^2 of IC space go to waste
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Amro Tork
06/17/2021, 6:28 AMHi @Weston Braun
Amro Tork
06/17/2021, 6:28 AMPlease contact me privately.
Amro Tork
06/17/2021, 6:29 AMWe can do a multi-project chip just like Matt Venn
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Konrad Wilk
06/17/2021, 11:47 AMI should add I have one based on Matt's as well. If you want to take https://github.com/konradwilk/caravel_user_project/ and put your design there and the testcases work (meaning you also put your verilog code, make sure to use one of the la lines to turn it on/off) , then go ahead.
Test cases are in verilog/rtl/test_sha1
Konrad Wilk
06/17/2021, 11:50 AMThe only gotcha is that I am on vacation this week and in rural area with little Internet so can't help much except at night (I am in EST imezone)
Konrad Wilk
06/17/2021, 12:21 PM@Amro Tork and @Weston Braun ^^ and also looking at the git log of my tree may give guidance on how different macros can be combined.