Weston Braun

06/17/2021, 3:06 AM
Its sorta last minute before the tapeout, but I am trying to to have ~ 5 mm^2 of IC space go to waste

Amro Tork

06/17/2021, 6:28 AM
Hi @Weston Braun
Please contact me privately.
We can do a multi-project chip just like Matt Venn

Konrad Wilk

06/17/2021, 11:47 AM
I should add I have one based on Matt's as well. If you want to take and put your design there and the testcases work (meaning you also put your verilog code, make sure to use one of the la lines to turn it on/off) , then go ahead. Test cases are in verilog/rtl/test_sha1
The only gotcha is that I am on vacation this week and in rural area with little Internet so can't help much except at night (I am in EST imezone)
@Amro Tork and @Weston Braun ^^ and also looking at the git log of my tree may give guidance on how different macros can be combined.