open-source-silicon.dev

When you run the pre-checker with `top` do you see it go over 64G? I mean it sounds unlikely, I give you that - but then your design from the sound of it is not exactly a small one?

Mine has 9 different SRAMs on it, and I believe that is likely flagging a lot of the DRC violations

I think you can avoid this by loading the maglef of the SRAMs during DRC check.

<@U0223CL4ASY> How do you tell it to do that?

Maybe you need to modify the drc.tcl in openlane/script/magic. This is my hack for one SRAM: <https://skywater-pdk.slack.com/archives/C016ULUQXDF/p1623297343025900?thread_ts=1623261561.023400&amp;cid=C016ULUQXDF>
You might need to use a loop to loop through all the SRAMs.

After using this, I still get a few DRC violations related to the metals around the SRAMs. Then, I set some blockages in GLB_RT_OBS to clear them.

<@U0223CL4ASY> thanks. By the way, I think I've said before the 4k and 8k are very experiential...

I may need to still divide the word line to get them working.

<@U0175T39732> Thanks for the info. Yes, I've changed it into 2kbyte SRAM