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#openlane
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# openlane
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Noah Moroze

06/29/2021, 8:31 PM
Hi all, I’ve been trying to understand a bit more about how LVS using Netgen works, and it looks to me like the OpenLANE flow performs this check by comparing a Verilog netlist outputted by OpenROAD with a Spice netlist extracted from the final design layout. I’m curious though why the flow doesn’t use the Verilog netlist output by Yosys after synthesis — wouldn’t that be closer to the intent of LVS, to ensure that OpenROAD doesn’t make any transformations that break from the original design?
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Matthew Guthaus

06/29/2021, 8:44 PM
There can be various things added after synthesis: PhysOpt, buffers, clocks, antenna diodes
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Mitch Bailey

06/29/2021, 10:38 PM
@Noah Moroze Just to expand on what Matthew Guthaus said, with LVS every device in the netlist extracted from the layout must match a device (or a cell in the case of LEF based layout) in the verilog (and possible combined spice library). I believe what you are thinking about is an equivalency checker that would compare netlists before and after synthesis to verify that the functionality is the same. I'm not sure what equivalency checker OpenRoad uses.
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Matthew Guthaus

06/29/2021, 10:52 PM
Technically, you could ignore some devices in LVS with the ignore keyword. OpenPhySyn (not PhysOpt, I was wrong) uses ABC for equivalence verification according to their paper, i believe
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Noah Moroze

06/30/2021, 3:24 PM
Gotcha, that makes sense — thanks!
I think I was thrown off a little by the writeup here: https://www.zerotoasiccourse.com/terminology/lvs/, cc @Matt Venn
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Matt Venn

06/30/2021, 3:28 PM
Thanks for the feedback
I'm not sure I get the difference though, isn't it the output of yosys with some extras added ( like the clock buffers), or was there something else that Didn't make sense in my definition?
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Noah Moroze

06/30/2021, 4:42 PM
@Matt Venn Sorry, I think I should have been a bit more specific. The issue is mostly that I took “with the one we get after the synthesis step” a bit too literally. I think I ended up confusing LVS with something more like LEC (like Mitch said), where I thought LVS was testing all of the OpenROAD steps. The thing I hadn’t really considered is that the netlist is ultimately produced by Yosys and OpenROAD, and LVS is just testing that the layout generated by OpenROAD matches what it thinks the netlist is (i.e. it’s not testing the correctness of the netlist additions that OpenROAD makes). I think it’s a subtle difference though.  Maybe a wording change along the lines of “… can compare this extracted netlist with the netlist OpenLANE used to generate the layout.” would be helpful.
(By the way, thanks so much for producing this resource and making it available — it’s been incredibly helpful for learning about ASIC design and demystifying a lot of things that otherwise felt really inaccessible!)
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Matt Venn

06/30/2021, 4:58 PM
I'll try to clarify the page a bit and then it would be great if you could give me feedback on whether you think that would have helped more