Hi, everyone. I am trying to connect my module with the top module user_analog_project_wrapper(caravan). The supply voltage of my module is 3.3V and I would like to use lv2hv level converter in hvl library to convert the input signal from 1.8v to 3.3v. I tried to insert lv2hv into my top-level verilog file but I got an error. The level converter verilog includes the cell udp_pwr_good_pp and that cell is defined as "primitive" which causes error in yosys. Does anyone know how to solve this issue or if there is other method to use this lv2hv cell? Thank you.

@mshalan @Tim Edwards can you guys help? We have too many level shifters I think to try that manually

@Shuo Lai: If you're using the

open_pdks

install, then there is a file

primitives.v

that you need to include in the verilog.

@Tim Edwards I already include the file

primitives.v

in my top-level verilog. I think the issue is that yosys cannot recognize the keyword "primitive". It gives error

ERROR: syntax error, unexpected TOK_ID

.

@Shuo Lai: You don't want yosys to deal with the primitives, only iverilog for simulation. For synthesis, I think you don't want to be defining either

FUNCTIONAL

or

USE_POWER_PINS

.

@Tim Edwards Thank you for your help and your patience. I find the cell

sky130_fd_sc_hvl__lsbufhv2lv_1

in

sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib

The lib is also automatically included in the config.tcl. (Showed in the image.) But I still got the error message from yosys `ERROR: Module `\sky130_fd_sc_hvl__lsbufhv2lv_1' referenced in module `\user_analog_project_wrapper' in cell

\level_converter' is not part of the design.

I think I must miss something. Not sure if you have any idea on this?

@Shuo Lai can you open the .lib and check if the cell is there?

@mehdi I check the .lib and the cell is there.

@Shuo Lai: I assume this is a problem of needing to declare the HVL library as the synthesis target for mapping, when running OpenLane.

@Tim Edwards Hello, I think I include the HVL library in the config.mk, just like in the first and second figure. But it still doesn't work and gives the error in the third image. Is it because I don't include it correctly? Should I include something else? I will be appreciate if you can give me some advice on what command I should use. Thanks!

I am not an OpenLane expert. You should probably flag one of the OpenLane developers like @Manar Abdelatty.

@Peijun Hou You need to set

SYNTH_READ_BLACKBOX_LIB

to one so that yosys will treat the hvl cell as a black box and won't complain that it isn't part of the design

Thanks, the command works for the design!