Does openlane or openroad include a verilog linter?
I'm doing back-end verification on the mpw-2 extracted spice netlists and am detecting unconnected input errors in several designs. Last year, I found the same type of errors in the caravel framework.
It seems that this type of error would be easily detectable in the gate level verilog. For example, unconnected
input
ports could flag a fatal error which could be overridden on a case-by-case basis.
Opinions?