Does openlane or openroad include a verilog linter? I'm doing back-end verification on the mpw-2 extracted spice netlists and am detecting unconnected input errors in several designs. Last year, I found the same type of errors in the caravel framework. It seems that this type of error would be easily detectable in the gate level verilog. For example, unconnected

input

ports could flag a fatal error which could be overridden on a case-by-case basis. Opinions?

the more basic checks like this the better IMO.

@Matt Venn Thanks for the response. Of course, back-end checks are always necessary, but wouldn't this be simple to implement in both the synthesis and routing stages, also. Synthesis would catch problems with the user specification, while routing would catch synthesis problems.