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openlane generates the powered verilog file that's then used for LVS. Is there a way to generate the verilog from the GDS? I can extract the spice netlist, but is there a way to convert that verilog?

Years ago I did something like that. Extracted compiled ROM modules to spice, converted that to verilog, and then simulated the verilog to verify that the layout was correct for each memory address. Some of the analog circuitry required tweaking. With openlane, it should be pretty straight forward.

<@U0172QZ342D> Here's a simple script I just wrote to convert the `user_project_wrapper` extracted spice to verilog.
It doesn't handle the input/output/inout declarations but you could probably pull those from the gate level verilog. Also passing bus signals to instances isn't pretty. `spi2v.sh &lt;spice_file&gt;` (Disclaimer: haven't tested the  verilog!)
```cat spi2v.sh
#! /bin/sh

awk '
/^.subckt/ {
	if ( $2 ~ /sky130/ ) {
		subckt = $2;
		module = 0;
	} else {
		subckt = $2;
		module = 1;
	}
	$1 = "";
	$2 = "";
	ports[subckt] = $0;
	getline;
	while ( /^+/ ) {
		$1 = "";
		ports[subckt] = ports[subckt] $0;
		getline;
	}
	if ( module == 1 ) {
		print "module", subckt, "(";
		expandedPortCount = split(ports[subckt], expandedPortList);
		lastPort = "";
		delete minBusIndex;
		delete maxBusIndex;
		portCount = 0;
		delete portList;
		for ( portIndex = 1; portIndex &lt; expandedPortCount; portIndex++ ) {
			arrayCount = split(expandedPortList[portIndex], bus, /[\[\]]/);
			if ( ! (bus[1] in minBusIndex) ) {
				portCount += 1;
				portList[portCount] = bus[1];	
				minBusIndex[bus[1]] = bus[2];
				maxBusIndex[bus[1]] = bus[2];
			}
			if ( arrayCount &gt; 1 ) {
				minBusIndex[bus[1]] = min(minBusIndex[bus[1]], bus[2]);
				maxBusIndex[bus[1]] = max(maxBusIndex[bus[1]], bus[2]);
			}
		}
		for ( portIndex = 1; portIndex &lt; portCount; portIndex++ ) {
			print "	" portList[portIndex] ",";
		}
		print "	" portList[portCount] ");"
		for ( portIndex = 1; portIndex &lt; portCount; portIndex++ ) {
			net = portList[portIndex];
			if ( minBusIndex[net] == "" ) {
				print "	input", net ";";
			} else {
				print "	input [" maxBusIndex[net] ":" minBusIndex[net] "]", net ";";
			}
		}
	}
}
module == 1 &amp;&amp; /^X/ {
	while ( /^X/ ) {
		instance = $1;
		$1 = "";
		nets = $0;
		subckt = $NF;
		getline;
		while ( /^+/ ) {
			$1 = "";
			nets = nets $0;
			subckt = $NF;
			getline;
		}
		portCount = split(ports[subckt], portList);
		netCount = split(nets, netList) - 1;
		if ( portCount != netCount ) {
			print "ERROR: net count match subckt/instance", portCount "/" netCount;
		}
		print subckt, instance, "(";
		for ( netIndex = 1; netIndex &lt; netCount; netIndex++ ) {
			print "	." portList[netIndex] "(" netList[netIndex] "),";
		}
		print "	." portList[netCount] "(" netList[netCount] "));";
	}
}
module == 1 &amp;&amp; /^.ends/ {
	print "endmodule";
}
function min(a, b) {
	if ( a &lt; b ) return a; else return b;
}
function max(a, b) {
	if ( a &gt; b ) return a; else return b;
}
' $1```