https://open-source-silicon.dev logo
Channels
Powered by
#openlane
Title
# openlane
p

Peijun Hou

09/18/2021, 5:55 PM
Hello. I want to thank Manar for the update on common_pdn.tcl. After the update of @User  , I run my design with macro and get the error in the following figure. My macro includes a sensor and sky130_sram_4kbyte_1rw1r_32x1024_8. sensor use VDD and VSS as power pin and sram use vccd1 and vssd1 as its power pin. So I change the "set macro" in common_pdn.tcl as follows.
set macro {
orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
power_pins "vccd1 VPWR VDD"
ground_pins "vssd1 VGND VSS"
blockages "li1 met1 met2 met3 met4"
straps {
}
Could anyone share suggestion and advice on this error? Thanks!
m

Manar Abdelatty

09/18/2021, 5:59 PM
@Peijun Hou You can try skipping the pdn check by setting 
FP_PDN_CHECK_NODES
to 0, it will bypass this step and if there is an issue with the pdn connection it will be flagged by LVS
m

Matthew Guthaus

09/19/2021, 12:39 AM
We should consider setting this to 0 by default. Does it ever actually help?
@Manar Abdelatty ^^
p

Peijun Hou

09/19/2021, 12:40 AM
@Matthew Guthaus No it doesn't for me
And I also want to ask, if my macro has power strip, should I insert core_macro_grid for my design? Like, should I insert it to stuff like sky130_sram_4kbyte_1rw1r_32x1024_8? I infact set FP_PDN_ENABLE_MACROS_GRID to 0 but the step in the figure is still performed. Not sure how to disable it
m

Matthew Guthaus

09/19/2021, 1:03 AM
I had to disable it too...
m

Manar Abdelatty

09/19/2021, 10:53 AM
@Matthew Guthaus It helps only when the pdn isn't connected as it will flag it, but I have seen it take long run time with large designs and multiple power domains.
@Peijun Hou If you set 
FP_PDN_ENABLE_MACROS_GRID
to 0 it will disable connecting the macros to the top level grid, but it will specify a macros grid without the connect statement so that pdngen doesn't draw vertical straps over your macros.
p

Peijun Hou

09/19/2021, 5:22 PM
@Manar Abdelatty Thank you. Could you also share suggestions on the LU factorization problem? Since it seems that setting 
FP_PDN_CHECK_NODES
 to 0 won't stop it.
m

Manar Abdelatty

09/19/2021, 6:14 PM
@Peijun Hou Sorry it seems to be related to the IR drop calculation, you can disable it by setting 
FP_PDN_IRDROP
to 0
p

Peijun Hou

09/20/2021, 6:17 PM
@Manar Abdelatty Thanks. Looks like it work. May I ask what should I do with this error?
m

Manar Abdelatty

09/21/2021, 12:44 PM
@Peijun Hou It is probably because of the warning before it that global routing finished with an overflow. You can try increasing the die area to see if it helps
Powered by