Hi all, Any ideas to solve my hold violation problem?

Antenna Summary:
Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/41-antenna.rpt
Number of pins violated: 25
Number of nets violated: 25
[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv
[INFO]: There are no max slew violations in the design at the typical corner.
[ERROR]: There are hold violations in the design at the typical corner. Please refer to /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/26-spef_extraction_sta.min.rpt.
[INFO]: Calculating Runtime From the Start...
[INFO]: flow failed for user_proj_example/2021.10.31_13.43.15 in 0h27m31s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_proj_example
Run Directory: /project/openlane/user_proj_example/runs/user_proj_example

Hi @User I had the same issue, the solution was to to change the clock uncertainty in my sdc file

Hi @User Thanks a lot for your help. Would you mind gimme an example of that and may I know how the change of the clock-uncertainty may effect the hold violation result? Are the tools (e.g. Yosis) going to use different gates (e.g. bigger/smaller buffers or inverters) to solve the issue?

Hi @User take a look at scripts/base.sdc in Your OpenLane folder

advice from efabless about clock violations: https://docs.google.com/document/d/13J1AY1zhzxur8vaFs3rRW9ZWX113rSDs63LezOOoXZ8/edit#

Hi @User, I am learning as well, what I have done I have changed my uncertainty to the values proposed by efabless in their new sdc

yes we're seeing slew and capacitance violations

yes it is, in scripts/base.sdc

can you link me the info you found about making changes for clock uncertainty?

@User @User Well, I solved the issue by setting the following options in the configuration file:

set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8

but where did you find the numbers?

@User so there is no much science in my changes, previously I have had the value set to 0.1 and efabless uses 0.25 so i Have updated my file and It helped to meet the timing

@User For “slew violation” I’d recommend you to make the core size bigger and also degrease the density by changing:

set ::env(PL_TARGET_DENSITY) 0.2

and the previous value I used was based on some example of Synopsys flow

to me this seems like the tools tell you the design will fail hold, so you change the margin and now it passes. But that doesn't seem like a great way of solving the issue. What if the margin is what it is for a good reason?

@User I can not make it bigger I want to pack it into a 1000x150 rectangle

@User I think this option would make the clock arrival time to the cell slower by placing the cell somewhere else. So it wont cause bad things happen. However it’s just a guess…

@User "Just Do It!!" 😀 Look I was afraid as well however is as much important as RTL modeling. In RTL you model the functional behavior issues and on STA time behavior and booth are important. The synthesis gives You network of gates based on Your RTL model and OpenSTA together with resizer make Your timing to be fulfilled based on SDC constraints

ah, so the sdc file configures the clock setup? rather than is the configuration for opensta?

as far as I know it configures STA and STA gives results. Based on those results resizer does its job