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#openlane
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# openlane
m

manili

10/31/2021, 2:25 PM
Hi all, Any ideas to solve my hold violation problem?
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Antenna Summary:
Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/41-antenna.rpt
Number of pins violated: 25
Number of nets violated: 25
[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv
[INFO]: There are no max slew violations in the design at the typical corner.
[ERROR]: There are hold violations in the design at the typical corner. Please refer to /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/26-spef_extraction_sta.min.rpt.
[INFO]: Calculating Runtime From the Start...
[INFO]: flow failed for user_proj_example/2021.10.31_13.43.15 in 0h27m31s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_proj_example
Run Directory: /project/openlane/user_proj_example/runs/user_proj_example
k

Krzysztof Herman

10/31/2021, 4:54 PM
Hi @User I had the same issue, the solution was to to change the clock uncertainty in my sdc file
m

manili

11/01/2021, 3:29 AM
Hi @User Thanks a lot for your help. Would you mind gimme an example of that and may I know how the change of the clock-uncertainty may effect the hold violation result? Are the tools (e.g. Yosis) going to use different gates (e.g. bigger/smaller buffers or inverters) to solve the issue?
k

Krzysztof Herman

11/01/2021, 12:34 PM
Hi @User take a look at scripts/base.sdc in Your OpenLane folder
the tool that mitigates the time violations is called resizer, and it is part of the openroad, You can take a look at scripts/openroad/or_resizer.tcl
the crucial step is to constrain the design
m

Matt Venn

11/01/2021, 2:25 PM
also we have the #timing-closure channel now
@User I am just learning this stuff, but wouldn't changing the clock uncertainty in base.sdc prevent the tools from doing the checks they are supposed to?
k

Krzysztof Herman

11/01/2021, 2:27 PM
Hi @User, I am learning as well, what I have done I have changed my uncertainty to the values proposed by efabless in their new sdc
I got rid of hold violations however I have something called "slew violation" and few antennas violations
m

Matt Venn

11/01/2021, 2:29 PM
yes we're seeing slew and capacitance violations
where did you find out about the new sdc file?
is that not in mpw-3a tagged tools?
k

Krzysztof Herman

11/01/2021, 2:30 PM
yes it is, in scripts/base.sdc
m

Matt Venn

11/01/2021, 2:52 PM
can you link me the info you found about making changes for clock uncertainty?
m

manili

11/01/2021, 3:05 PM
@User @User Well, I solved the issue by setting the following options in the configuration file:
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set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8
m

Matt Venn

11/01/2021, 3:07 PM
but where did you find the numbers?
k

Krzysztof Herman

11/01/2021, 3:07 PM
@User so there is no much science in my changes, previously I have had the value set to 0.1 and efabless uses 0.25 so i Have updated my file and It helped to meet the timing
m

manili

11/01/2021, 3:07 PM
@User For “slew violation” I’d recommend you to make the core size bigger and also degrease the density by changing:
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set ::env(PL_TARGET_DENSITY) 0.2
k

Krzysztof Herman

11/01/2021, 3:08 PM
and the previous value I used was based on some example of Synopsys flow
m

Matt Venn

11/01/2021, 3:08 PM
to me this seems like the tools tell you the design will fail hold, so you change the margin and now it passes. But that doesn't seem like a great way of solving the issue. What if the margin is what it is for a good reason?
k

Krzysztof Herman

11/01/2021, 3:08 PM
@User I can not make it bigger I want to pack it into a 1000x150 rectangle
I agree with @User about the changing the margins
as far as I know slew violations are related with the slope of the clock edge. I am wondering changinm my clock constrain just to make it " hold and setup violation less" at 120 % fclk what would make it work even better at fclk
m

manili

11/01/2021, 3:13 PM
@User I think this option would make the clock arrival time to the cell slower by placing the cell somewhere else. So it wont cause bad things happen. However it’s just a guess…
@User I usually consider changing the
sdc
a dangerous idea so solve the issues. So to be honest I really scare of doing that. 😁
k

Krzysztof Herman

11/01/2021, 3:21 PM
@User "Just Do It!!" 😀 Look I was afraid as well however is as much important as RTL modeling. In RTL you model the functional behavior issues and on STA time behavior and booth are important. The synthesis gives You network of gates based on Your RTL model and OpenSTA together with resizer make Your timing to be fulfilled based on SDC constraints
m

Matt Venn

11/01/2021, 3:21 PM
ah, so the sdc file configures the clock setup? rather than is the configuration for opensta?
k

Krzysztof Herman

11/01/2021, 3:22 PM
as far as I know it configures STA and STA gives results. Based on those results resizer does its job
of course SDC is considered when synthesis is done to run it under some constraints
I think that the clock frequency is considered first