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#openlane
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# openlane
r

Rodrigo Huerta Gañan

11/08/2021, 9:25 AM
Hi, I have the following error doing user_project_wrapper.
LVS Done.
LVS reports:
net count difference = 0
device count difference = 0
unmatched nets = 0
unmatched devices = 0
unmatched pins = 1
property failures = 0
Total errors = 1
[ERROR]: There are LVS errors in the design according to Netgen LVS.
I have added the pins into the module definition: ``ifdef USE_POWER_PINS`
inout vccd1,    // User area 1 1.8V supply
inout vssd1,    // User area 1 digital ground
``endif` and this into the module invocation ``ifdef USE_POWER_PINS`
.vccd1(vccd1),  // User area 1 1.8V power
.vssd1(vssd1),  // User area 1 digital ground
``endif` What can be wrong?
r

Rahul Bharadwaj

11/17/2021, 4:04 PM
Hello @User is this error solved?
r

Rodrigo Huerta Gañan

11/17/2021, 4:09 PM
Yes, we just did the macro bigger
r

Rahul Bharadwaj

11/17/2021, 4:10 PM
Ohh ok is the mismatched pin one of the supply pins?
r

Rodrigo Huerta Gañan

11/17/2021, 4:11 PM
Yes
r

Rahul Bharadwaj

11/17/2021, 4:11 PM
Ohh ok thank you for replying.
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