Hi, I have the following error doing user_project_wrapper.

LVS Done.

LVS reports:

net count difference = 0

device count difference = 0

unmatched nets = 0

unmatched devices = 0

unmatched pins = 1

property failures = 0

Total errors = 1

[ERROR]: There are LVS errors in the design according to Netgen LVS.

I have added the pins into the module definition: ``ifdef USE_POWER_PINS`

inout vccd1,    // User area 1 1.8V supply

inout vssd1,    // User area 1 digital ground

``endif` and this into the module invocation ``ifdef USE_POWER_PINS`

.vccd1(vccd1),  // User area 1 1.8V power

.vssd1(vssd1),  // User area 1 digital ground

``endif` What can be wrong?

Hello @User is this error solved?

Yes, we just did the macro bigger

Ohh ok is the mismatched pin one of the supply pins?

Yes

Ohh ok thank you for replying.