Mitch Bailey
11/08/2021, 9:42 AM<design>/runs/<tag>/results/lvs/<design>.*log
. Can you see which pin is giving the error?Krzysztof Herman
11/08/2021, 11:13 AMSubcircuit summary:
Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper
-------------------------------------------|-------------------------------------------
user_proj_example (1) |user_proj_example (1)
Number of devices: 1 |Number of devices: 1
Number of nets: 608 **Mismatch** |Number of nets: 609 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper
---------------------------------------------------------------------------------------
Net: vssd1 |Net: vssd1
user_proj_example/vssd1 = 1 | user_proj_example/vssd1 = 1
user_proj_example/vccd1 = 1 |
|
(no matching net) |Net: vccd1
| user_proj_example/vccd1 = 1
---------------------------------------------------------------------------------------
Netlists do not match.
Netlists do not match.
Magic DRC Summary:
Source: /project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/magic/36-magic.drc
Violation Message "Metal4 > 3um spacing to unrelated m4 < 0.4um (met4.5b) "found 32 Times.
Violation Message "This layer can't abut or partially overlap between subcells "found 51 Times.
Violation Message "Metal1 spacing < 0.14um (met1.2) "found 1734 Times.
Violation Message "Metal2 spacing < 0.14um (met2.2) "found 97 Times.
Violation Message "via4 width < 1.18um (via4.1 + 2 * via4.4) "found 1 Times.
Violation Message "Metal3 spacing < 0.3um (met3.2) "found 103 Times.
Violation Message "Metal4 spacing < 0.3um (met4.2) "found 27 Times.
Violation Message "poly overlap of poly contact < 0.08um in one direction (licon.8a) "found 146 Times.
Violation Message "Metal5 spacing < 1.6um (met5.2) "found 432 Times.
Violation Message "Via1 width < 0.26um (via.1a + 2 * via.4a) "found 2 Times.
Violation Message "via4 spacing < 0.42um (via4.2 - 2 * via4.4) "found 6 Times.
Total Magic DRC violations is 2631
Mitch Bailey
11/08/2021, 11:36 AMKrzysztof Herman
11/08/2021, 11:39 AMSubcircuit pins:
Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper
-------------------------------------------|-------------------------------------------
vssd2 |vccd1 **Mismatch**
vssd1 |vssd1
wb_clk_i |wb_clk_i
wb_rst_i |wb_rst_i
wbs_ack_o |wbs_ack_o
Mitch Bailey
11/08/2021, 11:59 AMuser_proj_example
, correct? I suggest you check that the vssd1 and vccd1 pins on user_proj_example
fit the grid for user_project_wrapper
.Krzysztof Herman
11/08/2021, 12:00 PMRodrigo Huerta Gañan
11/08/2021, 1:40 PMMitch Bailey
11/08/2021, 3:24 PMKrzysztof Herman
11/08/2021, 3:25 PMRodrigo Huerta Gañan
11/08/2021, 6:26 PMKrzysztof Herman
11/08/2021, 6:34 PMRodrigo Huerta Gañan
11/08/2021, 6:35 PMKrzysztof Herman
11/08/2021, 6:37 PMRodrigo Huerta Gañan
11/08/2021, 6:38 PMKrzysztof Herman
11/08/2021, 6:39 PMRodrigo Huerta Gañan
11/08/2021, 6:40 PMKrzysztof Herman
11/08/2021, 6:40 PMRodrigo Huerta Gañan
11/08/2021, 6:59 PM#mprj 1175 1690 N
chip_controller 1175 1690 N
with:
``ifdef USE_POWER_PINS`
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
``endif`
It gives me:
Subcircuit pins:
Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper
-------------------------------------------|-------------------------------------------
vssd2 |vccd1 **Mismatch**
vssd1 |vssd1
wb_clk_i |wb_clk_i
wb_rst_i |wb_rst_i
However with:
``ifdef USE_POWER_PINS`
.vccd1(vssa1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
``endif`
It works, and I'm not using analog, only digital things. I'm scared and I suppose that something is wrongKrzysztof Herman
11/08/2021, 7:02 PMRodrigo Huerta Gañan
11/08/2021, 8:57 PMMatt Venn
11/09/2021, 8:06 PM