Hello everyone, when I try to run openlane flow I ...
# openlane
m
Hello everyone, when I try to run openlane flow I get stuck when it tries to run ABC
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24.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-su8k8S/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-su8k8S/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-su8k8S/input.blif 
ABC: + read_lib -w /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.09 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use).  Time =     0.13 sec
ABC: Memory =    7.77 MB. Time =     0.13 sec
ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
ABC: + read_constr -v /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2".
ABC: Setting output load to be 33.442001.
ABC: + read_constr /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 50000.0 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + fraig_store 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + fraig_restore 
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 50000.0 
ABC: + buffer -N 5 -S 750.0 
ABC: + upsize -D 50000.0 
ABC: Current delay (0.00 ps) does not exceed the target delay (50000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 50000.0 
ABC: + stime -p 
ERROR: ABC: execution of command "/build/bin/yosys-abc -s -f /tmp/yosys-abc-su8k8S/abc.script 2>&1" failed: return code 139.
I can't even understand what the error is. Do you guys have some clue on how to solve it? Thanks in advance for the effort!
v
are you using openlane flow?
synthesis stage issue we need source verilog to debug or file github issue in yosys page
m
Yes, openlane flow
So it's better if I file an issue on GitHub
v
share ur config.tcl and verilog code
openlane version?
e
Exit code 139 is a segment fault. It means ABC tried to access memory it wasn’t supposed to when it was optimizing for timing. Are you running in a VM? I suspect it needs more memory.