Hi, I'm trying to harden my design for MPW4 but I every time I'm getting hold violations or capacitance violations. I'm using the OpenLane, efabless version with the MPW4 tag, I'm changing the parameters of PL_RESIZER_HOLD_SLACK_MARGIN,PL_RESIZER_MAX_SLEW_MARGIN,PL_RESIZER_MAX_CAP_MARGIN and PL_RESIZER_HOLD_MAX_BUFFER_PERCENT. But seems the result random every time I launched, some time I get violation in the sta_max other in the sta_min. Any suggestion of how better I can use that parameters, base of the violation time , or If i need another parameter to tweak, to get a hold free result?
12/29/2021, 9:16 AM
IF you wish raise git hub issue with source code and your requirements/ re-producible tar file
12/29/2021, 1:33 PM
Ok, now is solve I use the setting PL_TIME_DRIVEN to 1 and that finish without errors