STA in Openlane doesn't appear to incorporate any macro timing information. How are we guaranteeing a design with macros makes timing? Also wondering if OpenROAD supports loading multiple SPEF files.

You need to have a .lib for a macro. For multiple spefs - are you talking about hierarchical stitching or multiple corners?

So the .lib file IS considered during STA in Openlane automatically ? Thought that this is still worked on. What about the delays at the IOs of the macros ? For example, I don’t see data-in and data-out arcs of SRAMs in the 21-user_proj_example.sdf file.

@User I'm just fishing around, trying to work out how to do a full STA of my design. I found caravel is doing something similar to what I want: https://github.com/efabless/caravel/blob/main/Makefile#L625

@User this might be useful for you, I wrote it up for caravel https://docs.google.com/document/d/1sRZSxMVv12jqYFcXStf5rAlsCzi_GL__GNtekHq9XeA/edit?usp=sharing

Thanks @User