I'm still exploring how to use the SRAM macros wit...
# openlane
I'm still exploring how to use the SRAM macros with the complete flow. Thus, I started with simply changing the vanilla caravel_user_project repo's user_proj_example.v file to instantiate an SRAM macro instead of the default counter as follows.
Copy code
sky130_sram_1kbyte_1rw1r_8x1024_8 sram(
      .clk0  (clk)         ,// clock
      .csb0  (1'b0)        ,// active low chip select
      .web0  (io_in[8])    ,// active low write control
      .wmask0(io_in[12:9]) ,// write mask
      .addr0 (io_in[22:13]),
      .din0  (io_in[7:0])  ,
      .dout0 (io_out[7:0]) ,
      .clk1  (clk)         ,// clock
      .addr1 (io_in[31:22]),                                     
      .dout1 (io_out[15:8])
Find blackbox declaration and include it into your design + LEF + GDS + LIB. Should be enough
EXTRA_LEF and EXTRA_GDS and some other configs need to be set
I'm looking at @User application from MPW3: https://github.com/VLSIDA/openram_testchip/tree/main/verilog/rtl
so yes, agree with Arman, you need to copy the verilog, lef, gds
Thanks a lot Matt and Arman for providing the fix. I did get past the initial error.