Anuj Dubey
03/07/2022, 4:03 PM4.1. Analyzing design hierarchy..
ERROR: Module `\sky130_sram_1kbyte_1rw1r_8x1024_8' referenced in module `\user_proj_example' in cell `\sram' is not part of the design.
[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /home/aanujdu/caravel_tut/caravel_example/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-synthesis.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
I also got a warning about the MGMT_AREA_ROOT variable.
Makefile41 warning: undefined variable 'MGMT_AREA_ROOT'
I am unsure of what to set it to.
Can someone please help me with the above issues?Mitch Bailey
03/07/2022, 4:13 PMcaravel_user_example
uses mgmt_core_wrapper
which includes an sram module. Maybe take a look at that config.tcl
.
If you haven't already, in caravel_user_example
, make install_mcw
.Ruediger Ehlers
03/07/2022, 4:29 PMMatt Venn
03/07/2022, 4:53 PMAnuj Dubey
03/07/2022, 5:21 PMRuediger Ehlers
03/07/2022, 5:41 PMAnuj Dubey
03/09/2022, 2:40 AM###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]
[INFO]: Setting RC values...
[INFO RSZ-0027] Inserted 34 input buffers.
[INFO RSZ-0028] Inserted 69 output buffers.
[INFO RSZ-0058] Using max wire length 2319um.
[INFO RSZ-0039] Resized 152 instances.
[INFO RSZ-0042] Inserted 173 tie sky130_fd_sc_hd__conb_1 instances.
[INFO DPL-0034] Detailed placement failed on:
[INFO DPL-0035] sram
[ERROR DPL-0036] Detailed placement failed.
Error: resizer.tcl, 78 DPL-0036
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer.tcl
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
I am not sure what is DPL 0036 exactly, or if there is documentation on a possible fix. Have you faced this error? Is it because of not creating a macro.cfg in the user_project's config.tcl? I didn't because I wasn't sure if I need it in the first approach--it doesn't exist in the caravel/user_proj_example directory by default (unlike the caravel/user_project_wrapper directory) and config.tcl file also didn't contain the set command (again unlike the tcl file of the wrapper module).Ruediger Ehlers
03/10/2022, 1:47 PMAnuj Dubey
03/10/2022, 1:48 PMMatt Venn
03/10/2022, 5:03 PMAnuj Dubey
03/10/2022, 6:11 PMRuediger Ehlers
03/11/2022, 9:36 AMMatt Venn
03/11/2022, 10:19 AMRuediger Ehlers
03/11/2022, 10:40 AMMatt Venn
03/11/2022, 11:05 AMAnuj Dubey
03/13/2022, 2:05 PMMatt Venn
03/13/2022, 2:21 PMAnuj Dubey
03/13/2022, 4:44 PMMatt Venn
03/13/2022, 4:45 PMAnuj Dubey
03/13/2022, 4:48 PMCreating placeholder cell definition for module sky130_sram_1kbyte_1rw1r_32x256_8.
Reading setup file /home/aanujdu/caravel_tut/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl
Comparison output logged to file /home/aanujdu/caravel_tut/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/29-user_project_wrapper.lef.log
Logging to file "/home/aanujdu/caravel_tut/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/29-user_project_wrapper.lef.log" enabled
Circuit sky130_sram_1kbyte_1rw1r_32x256_8 contains no devices.
Contents of circuit 1: Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 1 device instances.
Class: sky130_sram_1kbyte_1rw1r_32x256_8 instances: 1
Circuit contains 122 nets, and 525 disconnected pins.
Contents of circuit 2: Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 1 device instances.
Class: sky130_sram_1kbyte_1rw1r_32x256_8 instances: 1
Circuit contains 121 nets, and 525 disconnected pins.
Circuit 1 contains 1 devices, Circuit 2 contains 1 devices.
Circuit 1 contains 122 nets, Circuit 2 contains 121 nets. *** MISMATCH ***
Result: Netlists do not match.
Logging to file "/home/aanujdu/caravel_tut/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/29-user_project_wrapper.lef.log" disabled
LVS Done.
LVS reports:
net count difference = 1
device count difference = 0
unmatched nets = 1
unmatched devices = 0
unmatched pins = 0
property failures = 0
Total errors = 2
[ERROR]: There are LVS errors in the design according to Netgen LVS.
[INFO]: Calculating Runtime From the Start...
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_project_wrapper
Run Directory: /home/aanujdu/caravel_tut/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper
Source not found.
----------------------------------------
LVS Summary:
Source: /home/aanujdu/caravel_tut/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/29-user_project_wrapper.lvs.lef.log
net count difference = 1
unmatched nets = 1
Total errors = 2
----------------------------------------
Antenna Summary:
No antenna report found.
[INFO]: check full report here: /home/aanujdu/caravel_tut/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.
[INFO]: The failure may have been because of the following warnings:
[WARNING]: Skipping Tap/Decap Insertion.
[WARNING]: All internal macros will not be connected to power.
[WARNING]: All internal macros will not be connected to power.
[WARNING]: All internal macros will not be connected to power.
while executing
"flow_fail"
(procedure "quit_on_lvs_error" line 11)
invoked from within
"quit_on_lvs_error -log $count_lvs_log"
(procedure "run_lvs" line 80)
invoked from within
"run_lvs"
(procedure "run_lvs_step" line 11)
invoked from within
"[lindex $step_exe 0] [lindex $step_exe 1] "
(procedure "run_non_interactive_mode" line 55)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
puts_info "Note, that post_run_hook..."
(file "/openlane/flow.tcl" line 412)
Makefile:41: recipe for target 'user_project_wrapper' failed
make[1]: *** [user_project_wrapper] Error 1
make[1]: Leaving directory '/home/aanujdu/caravel_tut/caravel_example/openlane'
Makefile:69: recipe for target 'user_project_wrapper' failed
make: *** [user_project_wrapper] Error 2
Matt Venn
03/13/2022, 5:08 PMAnuj Dubey
03/13/2022, 5:16 PMMatt Venn
03/13/2022, 5:17 PMAnuj Dubey
03/13/2022, 5:20 PMMitch Bailey
03/13/2022, 8:25 PM/home/aanujdu/caravel_tut/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/29-user_project_wrapper.lef.log
for the net differences. If the problem is not obvious, you can post the last portion of the log that shows the errors here.Ruediger Ehlers
03/13/2022, 9:46 PMAnuj Dubey
03/13/2022, 11:34 PMsky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB
(
`ifdef USE_POWER_PINS
.vccd1 (vccd1),
.vssd1 (vssd1),
`endif
.clk0 (user_clock2),
.csb0 (1'b0),
.web0 (wbs_we_i),
.wmask0 (wbs_sel_i),
.addr0 (wbs_adr_i[7:0]),
.din0 (wbs_dat_i),
.dout0 (la_data_out[31:0]),
.clk1 (user_clock2),
.csb1 (1'b0),
.addr1 (wbs_adr_i[15:8]),
.dout1 (la_data_out[63:32])
);
openram_1kB 344 475.5 N
for starters. Maybe I'll retry with (100, 100) as you had mentioned previously.Mitch Bailey
03/14/2022, 1:50 AMAnuj Dubey
03/14/2022, 3:58 AMMitch Bailey
03/14/2022, 5:07 AMuser_project_wrapper.gds
first? Do you have klayout?
1. Open the gds
2. set the top cell to sky130_sram_1kbyte_1rw1r_32x256_8
3. search for csb*
text
4. remember the location
5. set the top cell to user_project_wrapper
6. check the csb*
locations from the previous stepAnuj Dubey
03/14/2022, 3:21 PMMatt Venn
03/14/2022, 3:25 PMAnuj Dubey
03/14/2022, 3:27 PM[ERROR]: There are LVS errors in the design according to Netgen LVS.
[ERROR]: Flow failed.
Matt Venn
03/14/2022, 3:28 PMMitch Bailey
03/14/2022, 3:29 PMAnuj Dubey
03/14/2022, 3:33 PMMatt Venn
03/14/2022, 3:37 PMAnuj Dubey
03/14/2022, 3:37 PMMatt Venn
03/14/2022, 3:38 PMAnuj Dubey
03/14/2022, 3:50 PMMatt Venn
03/14/2022, 3:50 PMAnuj Dubey
03/14/2022, 3:53 PMmodule user_project_wrapper #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
// Independent clock (on independent integer divider)
input user_clock2,
// User maskable interrupt signals
output [2:0] user_irq
);
sky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB
(
`ifdef USE_POWER_PINS
.vccd1 (vccd1),
.vssd1 (vssd1),
`endif
.clk0 (user_clock2),
.csb0 (1'b0),
.web0 (wbs_we_i),
.wmask0 (wbs_sel_i),
.addr0 (wbs_adr_i[7:0]),
.din0 (wbs_dat_i),
.dout0 (la_data_out[31:0]),
.clk1 (user_clock2),
.csb1 (1'b0),
.addr1 (wbs_adr_i[15:8]),
.dout1 (la_data_out[63:32])
);
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
endmodule // user_project_wrapper
`default_nettype wire
Matt Venn
03/14/2022, 3:57 PMAnuj Dubey
03/14/2022, 4:01 PMuser_project_wrapper
----------------------------------------
Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d)
----------------------------------------
823.470um 557.860um 823.560um 558.260um
823.470um 556.050um 823.560um 558.260um
823.470um 556.040um 823.560um 556.050um
823.470um 555.760um 823.560um 556.040um
823.470um 555.750um 823.560um 555.760um
823.470um 549.700um 823.560um 550.100um
823.470um 547.890um 823.560um 550.100um
823.470um 547.880um 823.560um 547.890um
823.470um 547.600um 823.560um 547.880um
823.470um 547.590um 823.560um 547.600um
823.470um 542.900um 823.560um 543.300um
823.470um 541.090um 823.560um 543.300um
823.470um 541.080um 823.560um 541.090um
823.470um 540.800um 823.560um 541.080um
823.470um 540.790um 823.560um 540.800um
823.470um 857.060um 823.560um 857.460um
823.470um 856.625um 823.560um 857.460um
823.465um 856.600um 823.560um 856.625um
823.465um 856.320um 823.490um 856.600um
823.490um 856.320um 823.560um 856.600um
823.465um 856.295um 823.560um 856.320um
----------------------------------------
[INFO]: COUNT: 21
[INFO]: Should be divided by 3 or 4
Matt Venn
03/14/2022, 4:17 PMAnuj Dubey
03/14/2022, 4:19 PM[ERROR]: There are violations in the design after Magic DRC.
[ERROR]: Total Number of violations is 21
[ERROR]: Flow failed.
Matt Venn
03/14/2022, 4:19 PMAnuj Dubey
03/14/2022, 4:28 PMMatt Venn
03/14/2022, 4:53 PMAnuj Dubey
03/14/2022, 4:55 PMMatt Venn
03/14/2022, 4:55 PMAnuj Dubey
03/14/2022, 5:00 PMMatt Venn
03/14/2022, 5:17 PMAnuj Dubey
03/14/2022, 8:24 PMMitch Bailey
03/14/2022, 8:53 PMset ::env(GLB_RT_OBS) "li1 0 0 2920 3520,
met1 344.0 475.5 823.78 873.0,
met2 344.0 475.5 823.78 873.0,
met3 344.0 475.5 823.78 873.0,
met4 344.0 475.5 823.78 873.0"
Anuj Dubey
03/15/2022, 12:05 PMMatt Venn
03/15/2022, 1:01 PM