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#openlane
Title
# openlane
h

Hadir Khan

04/01/2022, 3:35 AM
I am running the openlane flow with mpw-5c tag and the flow fails after some DRCs
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Run Directory: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper                                                                                
----------------------------------------                                                  

Magic DRC Summary:                                                                        
Source: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper/reports/finishing/drc.rpt                                                                                                                                                                                                                                                  
Violation Message "Metal4 > 3um spacing to unrelated m4 < 0.4um (met4.5b) "found 10 Times.                                                                                           
Violation Message "Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d) "found 174 Times.                                                                                          
Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 5245 Times.                                                                                      
Total Magic DRC violations is 5429                                                        
----------------------------------------                                                  

LVS Summary:                                                                              
Source: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/37-user_project_wrapper.lvs.lef.log                                                                                                                                                                                                                         
LVS reports no net, device, pin, or property mismatches.                                                                                                                             
Total errors = 0                                                                          
----------------------------------------                                                  

Antenna Summary:                                                                          
No antenna report found.                                                                  
[INFO]: check full report here: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv                                                                                                                                                                                                                   
[INFO]: Saving runtime environment...                                                     
[ERROR]: Flow failed.                                                                     
[INFO]: The failure may have been because of the following warnings:                                                                                                                 
[WARNING]: All internal macros will not be connected to power.                                                                                                                       
[WARNING]: All internal macros will not be connected to power.                                                                                                                       
[WARNING]: All internal macros will not be connected to power.                                                                                                                       


    while executing                                                                       
"flow_fail"                                                                               
    (procedure "quit_on_magic_drc" line 13)                                               
    invoked from within                                                                   
"quit_on_magic_drc -log $::env(drc_prefix).tr"                                            
    (procedure "run_magic_drc" line 31)                                                   
    invoked from within                                                                   
"run_magic_drc"                                                                           
    (procedure "run_drc_step" line 8)                                                     
    invoked from within                                                                   
"[lindex $step_exe 0] [lindex $step_exe 1] "                                              
    (procedure "run_non_interactive_mode" line 55)                                        
    invoked from within                                                                   
"run_non_interactive_mode {*}$argv"                                                       
    invoked from within                                                                   
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {                                                                                                      
        puts_info "Running interactively"                                                 
        puts_info "Note, that post_run_hook..."                                           
    (file "/openlane/flow.tcl" line 412)                                                  
make[1]: *** [Makefile:43: user_project_wrapper] Error 1                                                                                                                             
make[1]: Leaving directory '/home/mkhan33/openram_testchip/openlane'                                                                                                                 
make: *** [Makefile:69: user_project_wrapper] Error 2
I am not able to see a
final/verilog/gl
directory which has a GL netlist. I want to ignore these DRCs and run simulation on the GL. Is it possible?
v

Vijayan Krishnan

04/01/2022, 6:43 AM
@User I also had such magic drc violations for some mpw designs with mpw-5c tag. Try with latest openlane tag, may resolve this issue, has magic version also got updated now.
h

Hadir Khan

04/01/2022, 7:13 AM
The drc violations are acceptable when designs have openram srams. The point is that the flow should still create a powered gate level netlist.
v

Vijayan Krishnan

04/01/2022, 9:23 AM
can you share your
/home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper/cmds.log
I am not able to see a final/verilog/gl directory which has a GL netlist.
try search in runs/user_project_wrapper/tmp/finishing/*_powered_netlist.v_