How can I add a PMOS to my verilog code for openlane?

Are you asking about pmos primitives? They are not synthesizable

Yes!!

You can use something like below https://github.com/kunalg123/SystemDesignWorkshopCollaterals/blob/master/cmos_inverter.v But they are not synthesizable. So can't be used for PNR

Thanks for the answer. But its needs to be synthesizable for my design. How do i go about it? Like in there are pfets and nfets defined in sky130_fd_pr. How can i include them in my verilog code for openlane?

PFET's and NFET's are in general not synthesizable

Ohh Okay

@Surag P: Depending on what it is you're trying to do, any components you want can go into a "hard macro" and can be placed and routed with everything else. It will get dropped somewhere into the design with lots of space around it so that it doesn't interfere with the rows of the digital core, but it can be done (the best place to be asking these questions is the #openlane channel).

Ohh okay.How do i go about making the Hard Macro?