Just use Xilinx Vivado or other tool to synthesize your desi open-source-silicon #general

Channels

hdl21

caravel-documentation

unic-cass-23

pd-openlane-and-sky130

chipignite2206q_stanford_bringup

dynamic-power-estimation

fossee-iitb-google-sky130

coalition-for-digital-environmental-sustainability

vlsi101

magical

vlsi_verilog_using_opensource_eda

basebands

vlsi_verilog_using_opensoure_eda

digital-electronics-learners

open-microelectronics-textbook

announcements

mwcas-2023-rtl2silicon

system-verilog-learners

vlsi-learners-group

chilechipmakers

silicon-validation-private

openhighqualityresonators

opendataset-circuitnet-for-ml-tasks-in-vlsi-cad

generative-ai

community_denmark_dtu

Title

# general

Arman Avetisyan

01/19/2022, 4:44 PM

Just use Xilinx Vivado or other tool to synthesize your design to see how much resources you need

👍 1

ANMOL SAXENA

01/21/2022, 3:07 PM

Table.xlsx

Based on this, i multiplied the LUTs by 6 and got a rough estimate of 200,000 for being safe.

Arman Avetisyan

01/22/2022, 10:03 AM

I think your calculation is wrong. 25.8k is more reasonable.

Look at the Digikey and find an FPGA that can has that many slices. I would go with +50%, so around 45k slices

👍 1