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#riscv
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Tim 'mithro' Ansell

07/19/2020, 9:04 PM
@User I use wishbone mostly
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ALI AHMED

07/19/2020, 9:15 PM
Thanks, i think we should stick to wishbone. Another question, have u guys used debug in your RISC-V Silicon validated core? if yes can you share any implementation in opensource?