4th mile-stone - 35 RISC-V cores in 5-days - Can you believe it? This time, we decided, let's build an automated infrastructure where participants can check-in each line of their code. Thanks to @User for his amazing idea of configuring Classroom GitHub. And that's it. We had Makerchip IDE, TL-Verilog, Day wise Slack channels, Classroom GitHub and VSD-IAT - All of them so seamlessly integrated that every participant followed the loop and there you go. Out of 110 participants, 35 participants built entire basic RISC-V CPU core which is close to 30% participants, and all in 5-days Thanks to for his amazing Makerchip IDE and TL-Verilog which makes coding RISC-V CPU so simple. Now we are convinced about format of the VSD workshops where participants passionately work for 14hrs per day and don't even get tired. In-fact, they ask for more. That's amazing response. Look at images below, and we will also releasing participants GitHub Links very soon on our website. Read below blog for more details: https://www.linkedin.com/posts/kunal-ghosh-vlsisystemdesign-com-28084836_35-risc-v-cores-in-5-days-can-you-believe-activity-6706433772277121024-wq1Z/

From experience, 15hr/day is a good hard bound you should tell people to use for themselves, and expect to be doing no other projects during these days, this is a "time off from work" thing.

All I can say - At end of the day, everyone enjoyed building their own RISC-V core from zero. That's what mattered the most 😊