open-source-silicon.dev

Is anyone submitting a rocket-chip generated core?

they're all pretty large as far as i'm aware, not sure if you'd be able to fit them along with enough cache to make them useful

a functional Scala to GDSII tapeout would be very useful, regardless of whether or not it's considered 'useful' for a real application

I do plan to include some chisel-generated cores in my design (although chisel was designed as ASIC-first so it's been used for tapeouts a loooot)

but yeah it'll definitely be useful to make sure chisel works fine with the openlane flow

we are trying to put chisel generated RV32I core in user area...