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#riscv
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Troy Benjegerdes

11/21/2020, 5:56 PM
Is anyone submitting a rocket-chip generated core?
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Anish

11/21/2020, 8:46 PM
they're all pretty large as far as i'm aware, not sure if you'd be able to fit them along with enough cache to make them useful
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Troy Benjegerdes

11/23/2020, 7:04 PM
a functional Scala to GDSII tapeout would be very useful, regardless of whether or not it's considered 'useful' for a real application
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Anish

11/23/2020, 7:33 PM
I do plan to include some chisel-generated cores in my design (although chisel was designed as ASIC-first so it's been used for tapeouts a loooot)
but yeah it'll definitely be useful to make sure chisel works fine with the openlane flow
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ALI AHMED

11/24/2020, 4:51 PM
we are trying to put chisel generated RV32I core in user area...