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Hello I'm facing the issues in clearing LVS in th...
# ieee-sscs-dc-22
i
Hello I'm facing the issues in clearing LVS in the Top Level. Interconnects are connected but it still shows no matching net.
a
post schematic and layout
example that can cause this: the transistor is connected to inverters input instead of output. The number of nets will match, but not the nets themselves
i
IMG-20221013-WA0014.jpg,IMG-20221013-WA0013.jpg
a
maybe ph1 and ph2 is swapped? its a little bit to debug it with these pictures and with no annotation
+ i am not sure where xtg is in your design
i
Swapped these terminals multiple times.
Layedout 10 times.
a
1. take screenshot 2. annotate as much as you can 3. verify every nets connection 4. verify evey components connection also use the transistors instead of symbol version of transmission gate to improve the debugability
i
Okay I'll look into it.
a
also i dont see the inverter in the schematic
its sus because the tg has to have inverters or one more input. Are they verified?
i
Yes tG is verified. I also designed/Layout Subtractor. It's lvs was cleared.
t
The layout side of the LVS has the standard cell (clkinv) pins marked 
1
, 
2
, etc., which means that it is not picking up the pin names. Why?
i
Yes it's not picking up but for other designs. It picks up.
Need to update magic?
t
No, it should not be an issue with magic. How are you generating the layout netlist?
i
ext2spice lvs extract all ext2spice It always make my top-level, .subckt I have to remove that .subckt script always
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