Hello All, Last friday during the mentoring we had...
# ieee-sscs-dc-22
j
Hello All, Last friday during the mentoring we had a brief discussion on MOSCAP. I was trying to find info on the tradeoff between area and parasitics, but couldn't find much. Could you elaborate a bit more on this, or provide some references? Thanks in advance! @Boris Murmann @kassemmkk @Harald Pretl
h
A MOSCAP is either operated in inversion (using a “normal” P-MOSFET or N-MOSFET) or in accumulation (putting an NFET into an n-well; this can be done in basically all CMOS technologies but it can be a bit hard to convince the PDK that is a good thing, device recognition and all; some technologies have a ready-made device for that; in SKY130 I think the “varactors” are exactly that, but not sure, I would need to check the layout and do a bit of device simulation). Due to this nature, it is quite nonlinear (the usual C-V curve that is expected for a MOSFET), but very high density since the gate oxide is thin. It is really unsymmetric, and the bottom electrode (either a p- or n-well) has a large parasitic PN-junction to the substrate, which is often not modeled. Having said that, you can still use them in a high-cap-with moderate-linearity-requirements application, very often VDD-decoupling or filters with low corner frequencies. Hope that answers your question.
The best is to simulate the device in the intended circuit for performance, and see whether it is OK. There are also some tricks you can do to linearize the capacitor. We have used that recently, and if it works well describe it in a future paper.
j
thanks a lot @Harald Pretl! maybe the varactor option in it's maximum capacitance condition wouldn't be a bad idea, since we are against time... our application is DCDC flying cap, so I think linearity is not critical. FYI @Kevin Pizarro
... but maybe not possible because we are targeting 5V, so we'll have to use high-V devices
h
Yes, for 5V you need to go with the thick-ox devices. Maybe the safer bet in this case is to stack dual MIM and metal plates, using a sandwich of poly-li1-m1-m2-m3.
BTW, the second link has a picture of the MOSCAP varactor.
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j
Yes, that's what we do now but the caps are huge. We are looking into alternatives to increase the density.
I meant the stacked mim caps. The metal plates idea could also work, thanks!
h
What’s the value you need? and how many of them?
j
We were targeting 50mhz operación, but already at 1mhz we are having trouble with efficiency We currently have 8nf, we would like to increase it as much as possible
*operation, sorry
And we need 2 For the li to M3 sandwich, we can find the capacitive contribution using patasitic extraction, i guess?
h
If you make a sandwich of plates, only the lowest is of interest, so you need to extract (or hand calculate) the parasitic cap from
li1
to substrate. Depending on your needs, you can use bootstrapping: Put an n-well underneath, so you have control to which node the parasitic cap goes (the n-well). Now you can connect to a node which is good, or even actively drive that node to nullify the effect of the parasitic cap.
8nF is huge, BTW. With DC/DC there is no free lunch, I fear: Either you accept more voltage ripple, or increase the cap, or increase the switching frequency, or use multi-phase. Is using external caps an option? Witch 2 caps thats somewhere 2–4 pins, and at 1MHz the package parasitics should be very manageable.