Hi everyone, do openlane flow generate any .sch sc...
# openlaned
Deepak
09/27/2022, 12:44 PMHi everyone, do openlane flow generate any .sch schematic file for digital designs??
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Arman Avetisyan
09/27/2022, 1:36 PMno
Arman Avetisyan
09/27/2022, 1:37 PMOnly netlist and it used to generate the dot file (which is not the same as schematic)
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Deepak
09/27/2022, 1:42 PMokay , thank you @Arman Avetisyan.
Then for mixed signal designs , how we will be doing LVS with analog design used as in along with digital. for analog we have schematic and final layout/gds of full digital+analog design...Any idea on this??
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Arman Avetisyan
09/27/2022, 1:49 PM... with the netlist? ... with blackboxed cell?
At the end of the day lvs just compares two netlists, one of them generated from schematic tool
Arman Avetisyan
09/27/2022, 1:49 PMwhen you blackbox the cell it only compares the ports and their connections skipping the internals
Arman Avetisyan
09/27/2022, 1:50 PMJust include the openlane generated netlist into your final netlist that is used for lvs
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Deepak
09/27/2022, 3:35 PMokay @Arman Avetisyan thanks!
->"with the netlist? ... with blackboxed cell? "
yes with blackboxed cell in the schematic netlist
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Arman Avetisyan
09/27/2022, 3:39 PMThen just create the blackbox and use it in your netlist. I do not know how to make it as symbol in xschem, but I would check the documentaiton for that
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Deepak
09/27/2022, 3:56 PMOkay ,yes for analog part i have created symbol. I also don't know how to make symbol for digital design in xschem.
please let me know if you find anything in document.
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