Hi, when i run make user_project_wrapper ,step 40 LVS error, the log present that unmatched nets = 149 and net count difference = 9 , total errors = 158 , and i found some possible error come from PDN : [WARNING PDN-0110] No via inserted between met4 and met5 at (691.2700, 939.8400) - (692.4700, 939.9300) on vssd1 ,there are about 200 messages like that,only on vssd1 and vccd1 . Is there some tcl command i need to fix?

set ::env(FP_PDN_CHECK_NODES) 0

set ::env(FP_PDN_ENABLE_RAILS) 1set ::env(FP_PDN_HORIZONTAL_HALO) 30

set ::env(FP_PDN_VERTICAL_HALO) 30 set ::env(FP_PDN_VWIDTH) 1.6

is that possible to share your project repo link?

Sure,this is repo link:https://github.com/LvmhZhD/test_eFPGA.git @Vijayan Krishnan

As per LVS error its looks like 9 nets are open and unconnected. Are you able to trace those? Share GDS file.

@Vijayan Krishnan i can not trace those unconnected nets but unmatched nets,it is gds file.

@Mitch Bailey can you please check this LVS issue?

@Vijayan Krishnan yes，i run several times in different config, and got that same messages

9 mismatch

in some of those. Others have more mismatchs because of the wrong config perhaps like

FP_PDN_VPITCH

...

There are some shorts happening. As net count less comparing LHS and RHS

Net: inst_eFPGA_top.Inst_eFPGA.Tile_X8Y13_ |(no matching net)                          
  S_term_single/vccd1 = 1                  |                                           
                                           |                                           
Net: inst_eFPGA_top.Inst_eFPGA.Tile_X7Y13_ |(no matching net)                          
  S_term_single/vccd1 = 1                  |                                           
                                           |                                           
Net: inst_eFPGA_top.Inst_eFPGA.Tile_X5Y13_ |(no matching net)                          
  S_term_single/vccd1 = 1                  |                                           
                                           |                                           
Net: inst_eFPGA_top.Inst_eFPGA.Tile_X6Y13_ |(no matching net)                          
  S_term_DSP/vccd1 = 1                     |                                           
                                           |                                           
Net: inst_eFPGA_top.Inst_eFPGA.Tile_X9Y13_ |(no matching net)                          
  S_term_RAM_IO/vccd1 = 1                  |                                           
                                           |                                           
Net: inst_eFPGA_top.Inst_eFPGA.Tile_X4Y13_ |(no matching net)                          
  S_term_single/vccd1 = 1                  |                                           
                                           |                                           
Net: inst_eFPGA_top.Inst_eFPGA.Tile_X3Y13_ |(no matching net)                          
  S_term_single2/vccd1 = 1                 |

@Vijayan Krishnanok,thx.But i dont know why these no matching net occur? I need to modify the config or modify the verilog file?

Actually, looks like rather than shorts, the layout (left side) has more connections than the verilog (right side). This would indicate that the layout is missing connections, which is what your lvs report shows. The vccd1 ports of S_term_single, S_term_DSP, S_term_RAM_IO shown do not appear to be connected in the layout. Can you verify?

@Mitch Bailey Yeah, i found in the layout, vccd1 port is not connected with S_term_single,...,, it seemed i need to modify the vccd1's location?

It may be much more complicated than that. If the macro is short, you made need to connect with vertical straps. I think the limit was about 250um. Anything shorter or narrower than that may not be connected. You might be able to reposition the macros so they intersect with the correct power straps. I don’t know if it’s possible to connect some macros with vertical and others with horizontal straps on the same layout hierarchy. You can look in the pdn log - there should be error messages if the power connections can’t be made.

ok， i think i found the problem. thanks a lot for you and Vijayan Krishnan.