#375 Process Spec 0.2: HV-NMOS/HV-PMOS spec unclear statement about validity conditions. Issue created by smunaut I'm looking at the "Process Spec 0.2" document, specifically HV-PMOS (same issue for HV-NNOS). The first line reads "VGS ≤ 3,3V (Maximum) @ 27°C for LG ≥ 0,5 µm". But then all the specs say they are for gate length of 0.4u and the layout rules also says 0.4u min gate length. So what is that first line supposed to mean ? Aren't we supposed to use 0.4u gate length ? IHP-GmbH/IHP-Open-PDK