I'm looking at the "Process Spec 0.2" document, specifically HV-PMOS. The first line reads "VGS ≤ 3,3V (Maximum) @ 27°C for LG ≥ 0,5 µm". But then all the specs say they are for gate length of 0.4u and the layout rules also says 0.5u gate length.

Could you please rise an issue on github ? I will delegate it to the responsible person.