/----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.50+56 (git sha1 78960292d, g++ 11.4.0-1ubuntu1~22.04 -fPIC -O3)

yosys> read_verilog -sv /media/ssd/chip_datasets/sky130/incr_add/incr_add.v

1. Executing Verilog-2005 frontend: /media/ssd/chip_datasets/sky130/incr_add/incr_add.v
Parsing SystemVerilog input from `/media/ssd/chip_datasets/sky130/incr_add/incr_add.v' to AST representation.
Successfully finished Verilog frontend.

yosys> read_verilog -debug -sv /media/ssd/chip_datasets/sky130/incr_add/incr_add.v

2. Executing Verilog-2005 frontend: /media/ssd/chip_datasets/sky130/incr_add/incr_add.v
Parsing SystemVerilog input from `/media/ssd/chip_datasets/sky130/incr_add/incr_add.v' to AST representation.
Starting parse
Entering state 0
Stack now 0
Reducing stack by rule 1 (line 466):
-> $$ = nterm $@1 (1.1: )
Entering state 2
Stack now 0 2
Reading a token
Now at end of input.
LAC: initial context established for "end of file"
LAC: checking lookahead "end of file": R12 G8 R2 G1 S3
Reducing stack by rule 12 (line 488):
-> $$ = nterm design (1.1: )
Entering state 8
Stack now 0 2 8
Reducing stack by rule 2 (line 466):
   $1 = nterm $@1 (1.1: )
   $2 = nterm design (1.1: )
-> $$ = nterm input (1.1: )
Entering state 1
Stack now 0 1
Now at end of input.
Shifting token "end of file" (1.1: )
LAC: initial context discarded due to shift
Entering state 3
Stack now 0 1 3
Stack now 0 1 3
Cleanup: popping token "end of file" (1.1: )
Cleanup: popping nterm input (1.1: )
Successfully finished Verilog frontend.

yosys> hierarchy -check -top incr_add

3. Executing HIERARCHY pass (managing design hierarchy).
ERROR: Module `incr_add' not found!

yosys>

module incr_add (
    input [3:0] a,
    input [3:0] b,
    input clk,
    input reset,
    output [3:0] sum,
    output carry
);

reg [3:0] sum;
reg carry;

always @(posedge clk or posedge reset)
begin
    if (reset)
    begin
        sum <= 4'b0000;
        carry <= 1'b0;
    end
    else
    begin
        sum <= a + b + carry;
        carry <= (a + b + carry) > 4'b1111;
    end
end

endmodule

gcc --version
make --version
flex --version
bison --version
cmake --version
gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

GNU Make 4.3
Built for x86_64-pc-linux-gnu
Copyright (C) 1988-2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <<http://gnu.org/licenses/gpl.html>>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
flex 2.6.4
bison (GNU Bison) 3.8.2
Written by Robert Corbett and Richard Stallman.

Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
cmake version 3.24.2

CMake suite maintained and supported by Kitware (kitware.com/cmake).

1. Executing Verilog-2005 frontend: garbage/incr_add.v
Parsing SystemVerilog input from `garbage/incr_add.v' to AST representation.
Generating RTLIL representation for module `\incr_add'.
Successfully finished Verilog frontend

read_verilog -debug

ls -ltra /media/ssd/chip_datasets/sky130/incr_add/incr_add.v
-rw-rw-r-- 1 will will 399 Feb 26 22:51 /media/ssd/chip_datasets/sky130/incr_add/incr_add.v