Are there any alternatives to generating .lib files for a custom PDK besides Cadence Liberate? I'm part of a University course that tapes out to TSMC180nm, but my team is trying to generate a digital ASIC in openlane, rather than do layout by hand. However, it seems like the .lib files are long and would be hard to do by hand or build a custom script to fill it out. Our school has a Cadence license but we're not sure if we can set up Liberate; are there any other alternative software/methods for generating .lib files so that we can port them into a custom PDK for openlane?

Hi, for CMOS standard cells there's lctime: https://codeberg.org/librecell/lctime