Good day, I am trying to create a layout for my C...
# sky130
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Good day, I am trying to create a layout for my CMOS inverter design using Magic and so I generated the netlist after completing the schematics and checking that the simulations were accurate, and yeah, i imported the spice netlist into magic so as to create my layout from there instead of starting from scratch. And so the picture below shows metal1 with the magenta (very light purple) colour and then a part of my PMOS transistor showing below, basically, i want to connect the metal1 to both the bulk and the source of the PMOS transistor, but looking at the colours before me, I got a little confused, my source is showing the colour labelled as viali and I'm not too sure what the bulk colour represents in my own layout, but my concern is the source that's looking like viali, I was expecting something different. So basically, I need help in connecting the metal contact to the source and bulk of my PMOS transistor.
m
@Oyetunde Dotun Here’s the process stack for skywater 130. What you want to know is how the magic layers map to the process layers.
locali
is
li
in the process stack.
viali
is
mcon
. To connect
metal1
to
locali(li)
use
viali(mcon)
. To connect
locali(li)
to
pdiffusion(diffusion)
, use
pdcontact(licon).
To connect
locali(li)
to
ntap(diffusion)
use
ntapdiffcont(licon)
.
t
@Oyetunde Dotun: Drawing metal1 directly from the metal1 shape at the top to the source contact (assuming source on top and drain on bottom in the orientation of the transistor in the screenshot) will connect the two, because the transistor source and drain are already contacted up to metal1. The source is a stack of p-diffusion contact (
pdc
) and
mcon
(shown as "viali" because each layer has multiple names). The bulk (nwell) contact is an n-substrate diffusion contact (
nsc
). The easiest way to contact the nwell is to select the transistor and raise the generated cell dialog window (
Ctrl-p
) and then enter "100" for "Right guard ring via coverage" (this is in the original orientation of the device, which has been rotated 90 degrees, so I don't know if it's the right or left side of the ring, but add the contact on the same side as the transistor source and it will short together with the metal 1).
The source is already contacted up to metal 1 because the option "Source via coverage" in the dialog is "100" by default, since it's generally a bad idea to route on local interconnect, so good layouts will almost always contact up to metal 1.