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I am getting this error when trying the flow using IIC-OSIC tools. I am using the SG13G2 ASIC deisgn Template given <https://github.com/simi1505/SG13G2_ASIC-Design-Template|here>. Can anybody help? <@U02UAUGSQ22>

<@U044B8D5M6E> Can you please take a look?

<@U04T86PFUTU> Could you please open an issue here? <https://github.com/simi1505/SG13G2_ASIC-Design-Template>

<@U04T86PFUTU> Looking into your `1_1_yosys.log` there is the following error: `ERROR: Synthesized memory size exceeds maximum allowed bits 4096`. I am not sure why this is caused, but since yosys throws this it has nothing to do with the IIC-OSIC-TOOLS. You need to look into your Verilog to see which part causes this, and then try to understand why.

Okay I am also equally confused why this is happening, will try to see what I can do although I did open up an issue in the Template repo as you suggested. Will update if I am able to solve it :+1: Btw thank you for helping out