the file in sky130, used for pad placement in desi...
# openlane
a
the file in sky130, used for pad placement in designs. sky130_fd_io.v is not synthesizable in yosys. what to do? this file is crucial to add i/o pads
m
@Atoshe Islam Sumaya Are you adding i/o pads in the user area? The cells in
sky130_fd_io.v
should be considered as black-boxed had macros. Does adding this file to
VERILOG_FILES_BLACKBOX
fix the problem?
a
i want to add i/o pad to my design. this is my Verilog code. `default_nettype none module user_fir_filter #( parameter FILTER_LENGTH = 41, parameter DATA_WIDTH = 16, parameter COEFF_WIDTH = 16, parameter ACC_WIDTH = 32 )( inout vccd, // 1.8V power supply inout vssd, // Digital ground input clk, // Clock input (direct clk) input reset_pad, // Reset input input coeff_update_pad, // Coefficient update signal input [5:0] coeff_sel_pad, // Coefficient selection input input [15:0] new_coeff_pad, // New coefficient input input [15:0] din_pad, // Data input output [31:0] dout_pad, inout AMUXBUS_A, // Auxiliary multiplexer bus A inout AMUXBUS_B // Data output ); // Internal signals wire clk, reset, coeff_update; wire [5:0] coeff_sel; wire [15:0] new_coeff, din; reg [31:0] dout; // Additional internal signals for power and ground pads wire pad_clk; wire pad_reset; wire pad_coeff_update; wire pad_coeff_sel; wire pad_new_coeff; wire pad_din; wire pad_dout; // Updated Power Pad Instantiation sky130_fd_io__top_power_lvc_wpad vccd_i ( .P_PAD(vccd), // Connect to power .AMUXBUS_A(AMUXBUS_A), // Auxiliary multiplexer bus A (can be left unconnected if unused) .AMUXBUS_B(AMUXBUS_B) // Auxiliary multiplexer bus B (can be left unconnected if unused) ); // Ground Pad Instantiation sky130_fd_io__top_ground_lvc_wpad vssd_i ( .G_PAD(vssd), .AMUXBUS_A(AMUXBUS_A), .AMUXBUS_B(AMUXBUS_B) ); // IO Pad for clk (Clock input pad, renamed) sky130_fd_io__top_sio clk_i ( .PAD(pad_clk), // Connect to physical clock pad .IN(clk) // Internal clk signal (now directly using clk) ); // IO Pads for reset, coefficient update, coefficient select, data in sky130_fd_io__top_sio reset_pad_i ( .PAD(pad_reset), // Connect to physical reset pad .IN(reset) // Internal reset signal ); sky130_fd_io__top_sio coeff_update_pad_i ( .PAD(pad_coeff_update), // Connect to coefficient update pad .IN(coeff_update) // Internal signal ); sky130_fd_io__top_sio coeff_sel_pad_i ( .PAD(pad_coeff_sel), // Connect to coefficient select pad .IN(coeff_sel) // Internal signal ); sky130_fd_io__top_sio new_coeff_pad_i ( .PAD(pad_new_coeff), // Connect to new coefficient pad .IN(new_coeff) // Internal signal ); sky130_fd_io__top_sio din_pad_i ( .PAD(pad_din), // Connect to data input pad .IN(din) // Internal signal ); // IO Pad for dout (Data output) connected to physical pad sky130_fd_io__top_sio dout_pad_i ( .PAD(pad_dout), // Connect to physical pad .DM(3'b110), // Drive strength .HLD_H_N(1'b1), // Hold signal (inactive) .INP_DIS(1'b1), // Disable input buffer .IN(dout), // Connect internal dout signal (32-bit) to IN port .OUT(dout) // Connect dout signal to OUT port (for output) ); // FIR Filter Core reg [DATA_WIDTH-1:0] reg_x [0:FILTER_LENGTH-1]; // Input data registers (16-bit) reg [ACC_WIDTH-1:0] reg_y [0:FILTER_LENGTH-1]; // Output data registers (32-bit) reg [COEFF_WIDTH-1:0] coeff [0:FILTER_LENGTH-1]; // Filter coefficients (16-bit) reg [ACC_WIDTH-1:0] acc; // Accumulator (32-bit) integer i; always @(posedge clk or posedge reset) begin if (reset) begin dout <= 0; acc <= 0; for (i = 0; i < FILTER_LENGTH; i = i + 1) begin reg_x[i] <= 0; reg_y[i] <= 0; end end else begin if (coeff_update) begin coeff[coeff_sel] <= new_coeff; // Update coefficient based on select signal end else begin // Shift register for input data (FIFO behavior) for (i = FILTER_LENGTH-1; i > 0; i = i - 1) begin reg_x[i] <= reg_x[i-1]; end reg_x[0] <= din; // Load new data input // Compute the FIR filter output acc = 0; for (i = 0; i < FILTER_LENGTH; i = i + 1) begin reg_y[i] <= reg_x[i] * coeff[i]; // Multiply input with coefficient acc = acc + reg_y[i]; // Sum the result end dout <= acc; // Store the result in dout end end end endmodule ... during floorplan, it is giving this error. what to do? % run_floorplan [STEP 4] [INFO]: Running Initial Floorplanning (log: designs/user_fir_filter/runs/RUN_2025.01.20_07.39.39/logs/floorplan/4-initial_fp.log)... [INFO]: Floorplanned with width 192.74 and height 190.4. [STEP 5] [INFO]: Running IO Placement (log: designs/user_fir_filter/runs/RUN_2025.01.20_07.39.39/logs/floorplan/5-place_io.log)... [STEP 6] [INFO]: Running Global Placement (log: designs/user_fir_filter/runs/RUN_2025.01.20_07.39.39/logs/placement/5-global.log)... [ERROR]: during executing openroad script /openlane/scripts/openroad/gpl.tcl [ERROR]: Log: designs/user_fir_filter/runs/RUN_2025.01.20_07.39.39/logs/placement/5-global.log [ERROR]: Last 10 lines: [INFO GPL-0029] BinSize: ( 3.012 2.975 ) [INFO GPL-0030] NumBins: 4096 [NesterovSolve] Iter: 1 overflow: 0.000 HPWL: 900050 [INFO GPL-0100] worst slack 1e+30 [WARNING GPL-0102] No slacks found. Timing-driven mode disabled. [NesterovSolve] Snapshot saved at iter = 0 [INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0 [ERROR GRT-0010] Instance vssd_i is not placed. Error: gpl.tcl, 75 GRT-0010 child process exited abnormally [ERROR]: Creating issue reproducible... [INFO]: Saving runtime environment... OpenLane TCL Issue Packager EFABLESS CORPORATION AND ALL AUTHORS OF THE OPENLANE PROJECT SHALL NOT BE HELD LIABLE FOR ANY LEAKS THAT MAY OCCUR TO ANY PROPRIETARY DATA AS A RESULT OF USING THIS SCRIPT. THIS SCRIPT IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND.
I want this type of view of my design. please help
m
@Atoshe Islam Sumaya I don’t think the layout you have is available through efabless. Are you trying to create a design independently with the sky130 process? I couldn’t find the
IO_CONFIG
variable in the openlane environment variables. Is it new? You don’t have a
MACRO_PLACEMENT_CFG
file to tell where to place the macros.
a
Yes, i am trying to create it independently.Okay, there is no problem if I don’t get the desired layout. Can you help me with placing i/o pads in my design? There is an error above i am getting when trying to place pads
Sorry Sir, I understood. I need to place the macro_placement_cfg. Thanku very much
I am also using the IO_CONFIG for the first time in my design. Should i share the file?
m
Can you share the openlane documentation on the
IO_CONFIG
variable?
a
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