Hello, I am trying to simulate the verilog file generated after synthesis using a testbench. I will share the verilog netlist code, test bench, and using iverilog i am trying to simulate but i am not getting the output for the design(8-bit up counter). Do i need to make any changes? please advise I am getting these errors after simulation in Iverilog: PDK = sky130_fd_sc_hd PDK_ROOT = /home/katkoori/.volare Compiling... Running sim... Applying initial reset... VCD info: dumpfile waveform.vcd opened for output. Time = 0ns, clk = 0, rst = 1, count = x Time = 10ns, clk = 1, rst = 1, count = x Observing counter increment... Time = 20ns, clk = 0, rst = 0, count = x Time = 30ns, clk = 1, rst = 0, count = x Time = 40ns, clk = 0, rst = 0, count = x Time = 50ns, clk = 1, rst = 0, count = x Time = 60ns, clk = 0, rst = 0, count = x Time = 70ns, clk = 1, rst = 0, count = x Time = 80ns, clk = 0, rst = 0, count = x Time = 90ns, clk = 1, rst = 0, count = x Time = 100ns, clk = 0, rst = 0, count = x Time = 110ns, clk = 1, rst = 0, count = x Time = 120ns, clk = 0, rst = 0, count = x Time = 130ns, clk = 1, rst = 0, count = x Time = 140ns, clk = 0, rst = 0, count = x Time = 150ns, clk = 1, rst = 0, count = x Time = 160ns, clk = 0, rst = 0, count = x Time = 170ns, clk = 1, rst = 0, count = x Time = 180ns, clk = 0, rst = 0, count = x Time = 190ns, clk = 1, rst = 0, count = x Time = 200ns, clk = 0, rst = 0, count = x Time = 210ns, clk = 1, rst = 0, count = x Applying reset during operation... Time = 220ns, clk = 0, rst = 1, count = x Time = 230ns, clk = 1, rst = 1, count = x Observing counter after reset... Time = 240ns, clk = 0, rst = 0, count = x Time = 250ns, clk = 1, rst = 0, count = x Time = 260ns, clk = 0, rst = 0, count = x Time = 270ns, clk = 1, rst = 0, count = x Time = 280ns, clk = 0, rst = 0, count = x Time = 290ns, clk = 1, rst = 0, count = x Time = 300ns, clk = 0, rst = 0, count = x Time = 310ns, clk = 1, rst = 0, count = x Time = 320ns, clk = 0, rst = 0, count = x Time = 330ns, clk = 1, rst = 0, count = x Time = 340ns, clk = 0, rst = 0, count = x Time = 350ns, clk = 1, rst = 0, count = x Time = 360ns, clk = 0, rst = 0, count = x Time = 370ns, clk = 1, rst = 0, count = x Time = 380ns, clk = 0, rst = 0, count = x Time = 390ns, clk = 1, rst = 0, count = x Time = 400ns, clk = 0, rst = 0, count = x Time = 410ns, clk = 1, rst = 0, count = x Time = 420ns, clk = 0, rst = 0, count = x Time = 430ns, clk = 1, rst = 0, count = x counter_tb.v49 $stop called at 440000 (1ps) * VVP Stop(0) * ** Flushing output streams. ** Current simulation time is 440000 ticks.

@Ravi Teja Can’t offer any advice about the verilog simulation results, but your script is setting the

PDK

variable equal to the standard cell library. This might affect other programs. I think

PDK

should be set to

sky130A

, and then you can replace all instances of

PDK

with

STD_CELL_LIBRARY

which you should set to

sky130_fd_sc_hd

.

Thank you for the advice and I used the wrong netlist Verilog file. I just found out that I've to use powered netlist Verilog file which is in /designs/<design_name>/runs/full_guide/results/final/Verilog/gl/<design_name>.v. But I've another doubt like we do 3 simulations right. behavioral level, gate level and then post layout we'll be getting another file. I couldn't able to find the file after post layout. Can you please suggest if you know about this.

@Ravi Teja I don’t know of any post layout verilog files. There’s a post synthesis, post timing verilog file, but I think that’s the one you’re using. Normally, when I hear post layout, I think of the extracted spice netlist with parasitic capacitances and resistors. I that what you’re referring to?