Maybe interesting: We have created an open-source analog circuit design course using Xschem and ngspice, as well as using CACE as simulation runner and Jupyter notebooks for circuit sizing using gm/Id method. All materials, examples, xschem circuits, etc. are open-source. You are welcome to provide feedback or additions (via GH PR). We are using IHP open-source PDK as pure 130nm CMOS node. https://iic-jku.github.io/analog-circuit-design/

@Harald Pretl: FYI, work on integration of magic, netgen, and other tools into the IHP open PDK is ongoing; the first part of that work, which includes parasitic capacitance modeling and extraction in magic and LVS in netgen, will be finished next week and pushed back to IHP. The development work is in a fork of the IHP open PDK at github/efabless, if you want to take a look at it.

@Tim Edwards Great, really looking forward to that. How about pcells?

Not immediately; I plan to have generated cells in magic done by April.

That is great! I just can't work with klayout. I'm just waiting for the magic tech file to start making layouts for IHP.

@Luis Henrique Rodovalho: You can alpha test the Efabless fork, if you're willing to put up with occasional sudden unannounced changes. The fork is currently up-to-date with IHP's upstream respository.

The branch is `efabless_develop`: https://github.com/efabless/IHP-Open-PDK/tree/efabless_develop

Will there be a chipalooza for IHP? Is there a IP wish list for IHP?

Nothing immediate planned from the Efabless side, but I'm hoping we can revisit that next year.

Great Job Dr. @Harald Pretl this is really beneficial.

We aim to support analog for the 2025 IHP Tiny Tapeout

@Matt Venn: You are very brave. : )

@Harald Pretl this is great, thanks for sharing it! Practical question: which sw did you use for drawing schematics?

@Jorge Marin schemdraw, a Python Package (the schematics are actually programmed in Python)

I'll give it a try, many thanks!